PVTs and How They Impact Timing
Factors Affecting Delays of Standard Cells
Timing: Basics
Clock Gating
Sample Problem on Setup and Hold
Electrostatic Discharge vs Electromigration
Clock Gating Integrated Cell
Routing: Basics
Clock Gating Check
Clock Skew: Implication on Timing
OCV vs PVT
Clock Jargon: Important Terms
Low Power Synthesis: Insertion of Clock Gating Cells
Common Path Pessimism
Placement of Clock Gating Cells
Feature Size of Transistors
Timing Analysis: Graph Based vs Path Based
Latch-Up in CMOS
Inverter vs Buffer Based Clock Tree
Drain and Source of MOS transistors
Channel Length vs Gate Length
Hold Time Violations
IR Drop Analysis
Register Banking
Power Domain Crossings
OCV v/s AOCV
Factors Affecting Delays of Standard Cells
Timing: Basics
Clock Gating
Sample Problem on Setup and Hold
Electrostatic Discharge vs Electromigration
Clock Gating Integrated Cell
Routing: Basics
Clock Gating Check
Clock Skew: Implication on Timing
OCV vs PVT
Clock Jargon: Important Terms
Low Power Synthesis: Insertion of Clock Gating Cells
Common Path Pessimism
Placement of Clock Gating Cells
Feature Size of Transistors
Timing Analysis: Graph Based vs Path Based
Latch-Up in CMOS
Inverter vs Buffer Based Clock Tree
Drain and Source of MOS transistors
Channel Length vs Gate Length
Hold Time Violations
IR Drop Analysis
Register Banking
Power Domain Crossings
OCV v/s AOCV
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