Parallel to Serial Converter

Let's discuss the design of a Parallel to Serial Converter. Here's the crude problem statement.

You have 8 FFs, each working at a frequency of 10MHz and sending out a parallel data which effectively would be 8-bit wide. We intend to convert this data into a serial one, where 1 FF would output the data serially in order of first FF, then data of second FF and so on. Refer to the diagram below:

Such a parallel to serial converter might be useful in applications requiring Serial Communication which maybe interface to a microprocessor or a microcontroller; interface between your monitor and the CPU or any application which might involve serial processing of information.

Now let's proceed for the design. Note that:

• We have 8-bits of input data, and we want to output them one at a time. This suggests the use of a multiplexer. The size of this multiplexer would obviously be 8:1.
• Apart from the inputs, the multiplexer would have select lines (3 select lines for a 8:1 MUX) and we need to control these lines. Select lines need to be controlled in such a way that first the FF1 is selected, then FF2 and so on. 
• Recall the functionality of a multiplexer. The first bit is selected when select lines would be {S2,S1,S0} = 000, Second bit when {S2,S1,S0} = 001. Hence we can use a binary counter which would count from 000 to 111 in a binary manner.
• What would be the frequency of this counter? Note that for every one cycle of input data, we need to 8 outputs corresponding to 8 input FFs. Hence the frequency of the counter would be:

Freq. = 8 X 10 MHz = 80 MHz

Here's the final design:

Puzzle: Finite State Machine

I loved solving problems on Finite State Machines back in college days. Recently, I came across a good problem and thought it would be expedient to share it for you as well!

Q. The ACME Company has recently received an order from a Mr. Wiley E. Coyote for their all-digital Perfectly Perplexing Padlock. The P3 has two buttons ("0" and "1") that when pressed cause the FSM controlling the lock to advance to a new state. In addition to advancing the FSM, each button press is encoded on the B signal (B=0 for button "0", B=1 for button "1"). The padlock unlocks when the FSM sets the UNLOCK output signal to 1, which it does whenever the last N button presses correspond to the N-digit combination.

1. Unfortunately the design notes for the P3 are incomplete. Using the specification above and clues gleaned from the partially completed diagrams below fill in the information that is missing from the state transition diagram with its accompanying truth table. When done :
   • Each state in the transition diagram should be assigned a 2-bit state name S1S0 (note that in this design the state name is not derived from the combination that opens the lock),
   • The arcs leaving each state should be mutually exclusive and collectively exhaustive,
   • The value for UNLOCK should be specified for each state, and
   • The truth table should be completed.
   •  What is the combination for the lock?
     
     
   
   
    
   Source: MIT Course Ware 

Puzzle: Multiplexer Trees

Are you comfortable making multiplexer trees? If you are, then try this one:

How many 2:1 MUXes you would require to make any n:1 MUX, where n is any integer greater than or equal to 2.



Answer is n-1.

Solution:

By principle of mathematical induction, we can say that for any n:1 MUX, we would require (n-1) 2:1 MUXes.