Low Power Methodology

Need for Low-Power Design Methodology
Clock Gating
Clock Gating Integrated Cell
Power Gating
State Retention Power Gating
Multi-Cycle Paths: Perspective & Intent
Low Power FSMs
Low Power Synthesis: Insertion of Clock Gating Cells
Faulty Clock Gating: How not to gate the clock
Reversible Logic Gates
Integrated Clock and Power Gating
Self Gated FF