June 17, 2016

Self Gated Flip-Flop

Hey folks!

Just yesterday, I was wondering if it's possible to come up with a self gated flip-flop architecture which could be used to extreme low-power applications. As soon as I designed the flip-flop and satisfied myself that it seemed to be working well on paper, I was ecstatic! However, that was short-lived because a prior art search revealed that someone had already designed a pretty similar structure 2 years back!

But since I found it cool, I'm tempted to share it with the readers here. Let's start with the motivation for such a flip-flop.

There may be applications in which certain flip-flops of the design may toggle states quite infrequently. Now, it's a well known fact that even though a flip-flop is not switching states, it will continue to dissipate dynamic power internally as long as the clock is constantly switching states. And there's also a well-known, exalted solution of clock gating! But clock gating is not always a viable solution. Let's look at the reasons when and why clock gating may not be a viable solution:

Clock Gating Integrated Cell
  • Clock Gating is usually performed by using a clock gating integrated cell, which essentially comprises of a latch and an AND gate. Latch itself is a sequential element, and logically half of the flip-flop, and physically takes up around 60-65% of the flip-flop area. Coupled with an AND gate, the internal switching activity of the clock gating cell would result in significant standby power dissipation.
  • Adding a clock gating cell makes sense only if there are a bunch of flip-flops to be clock gated. That is basically to offset the extra overhead of power dissipation within a clock gating cell.
  • Clock Gating cell will also have additional logic to control it's enable signal, leading to more power dissipation, however, this component is not really significant in most of the cases.

All the above reasons point for need of an effective strategy for a fine-grained clock gating technique without worrying about any additional overheads one might incur in doing so. That way a self-gated flip-flop might come to our rescue and would help in saving that extra milli- or perhaps micro-watts of power! Pretty cool, no! ;)

Architecture:
What I thought was: flip-flop would have a state either 0 or a 1. And these are the only two states that one ever needs to worry about. And this is best accomplished by a toggle flop.

Toggle Flop


Now, let's say initially flip-flop was reset to 0 and D was 0. The flop should be self gated. And as soon as D goes to 1, the flip-flop should TOGGLE, and stay at 1 as long as D stays as 1. So, we need the following components: a toggle flop; a XOR between D, Q; and a clock gating logic (either an AND or an OR gate).

Connections are pretty intuitive as shown as follows:


Implementing XOR is simple, and can be accomplished by using 8 transistors plus inverters. NOR gate would need 4 additional transistors. So, using just 12 extra transistors on top of the existing flip-flop circuit, you get a self-gated flip-flop with minimal dynamic power! How's that for a circuit?!

Self-Gated FF

It would be prudent to add the name of the patent/publication that I eventually found in the references, so that nobody accuses me of plagiarism! :D

Reference: 


  • Low Power Toggle latch-based flip flop including integrated clock gating circuit: US 20150200652A1.

4 comments:

  1. Is the 'Self-gated FF' circuit correct ? The OR gate on the clock means FF will be toggling every clock.
    Shouldn't it be something like clk_eff = CLK & ( D ^ Q ) ?

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  2. http://www.ieeexpert.com/vlsi-phd-research-thesis/

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  3. Hi Naman I had some thoughts about these cell. Let me know if there is something that I have missed. After reading a lot about these pulse triggered flip flops for self gating I think it still doesn't implement the true QoR of power reduction.

    The number of cell nodes toggling with clock as an input is still near 4 (generic FF 2 NOT(major) and 4TG(minimal) and new ones using NoR nodes) and not to forget the added internal power overhead due to additional gate insertion.

    So in practice these implementation actually increase the overall dynamic power component (Switching is reduced marginally but internal short-circuit is exacerbated alot; not to mention area and timing degradation). These cells argue that frequency increase impacts switching more hence the savings but in reality the realistic operating frequencies of these cells is also compromised so that doesn't hold true.

    Moreover the pulse width and duty cycle signoff limitations just throw another wrench in the same along with some cell level race conditions which is why I think people have found it rather pleasant to ue either CG or recirculating flops instead.


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