March 01, 2017


When I had started my career around 6 years back, we were introduced to the term called OCV. While the OCV concept was quite simple and fascinating, it didn't me long to realize that OCV can be a nightmare for every STA engineer out there. I had introduced OCV long time back while explaining the difference between OCV v/s PVT. In this post, I intend to draw a distinction between OCV (On-Chip Variation) and AOCV (Advanced On Chip Variation).

Before we discuss anything about OCVs, it would be prudent to talk about the sources and types of variations that any semiconductor chip may exhibit.

The semiconductor device manufacturing process exhibit two major types of variations:

  • Systematic Variations: As the name suggests, systematic variations are deterministic in nature, and these can usually be attributed to a particular manufacturing process parameter like the manufacturing equipment used, or perhaps even the manufacturing technique used. Systematic variations can be experimentally calibrated and modeled. They also exhibit spatial correlation- meaning two transistors close to each other would exhibit similar systematic variation- which makes them easier to gauge. Example would be inter-chip process variations between two different batch of manufactured chips.
    When a certain technology is in its nascent stage (let's say 10-nm technology), the process engineers would typically be more concerned about these variations and as the technology matures, process engineers are able to calibrate and tune their manufacturing process to reduce this variation component.
  • Random Variations: These are totally random, and therefore non-deterministic in nature. Random variations do not show spatial correlation and therefore very difficult to gauge and predict. Unlike systematic variations, random variations usually have a cancelling effect owing to their random nature. Examples are subtle variations in transistor threshold voltage.
As the semiconductor node shrinks, the susceptibility to the variations increase. And the effect of these variations need to be taken into account while doing timing analysis, or perhaps during the overall design planning to some extent. Shifting our focus back to OCV and AOCV. At this time one may ask themselves in what form would these variations manifest themselves? Well, these variations can manifest themselves in form of increase or decrease in the threshold voltage of devices, shift the process of the manufactured devices, perhaps vary the oxide thickness or change the doping concentration..
There might be infinite such manifestations and we engineers like to make our lives easier, don't we? ;)
Experienced folks must have guessed where am I headed. If you haven't guessed it yet, stay with me, take a step back and what does all these parameters have in common? What's that one quantifiable metric that these will impact and the answer is the delay! OCV and AOCV are essentially models which guide us on how the cell delay varies in light of the systematic and random variations.

On-Chip-Variations (OCV): OCVs are simplistic and (generally) pessimistic view of modelling process variations. Here we use that the delay of all cells can show, let's say X% variation in their delays. Now you would either model this variation as -X% to +X%, or perhaps -(X/2)% to +(X/2)%. Let's say we choose the latter. Now we would model the delay of all cells and subject them to OCVs in a manner that our timing becomes pessimistic and we can claim that in the worst case, as long as process guys can ensure that the variation would be within the bracket of -X% to +X%, we'd be safe.

  • Setup Analysis under OCV: In order to make setup analysis immune to process variations on silicon, we need to model the OCVs such that setup check becomes more pessimistic. That would be the case if we increase the data path delay by X% (you can take a call whether or not to apply a derate on the net delays. One can choose to apply a net derate based on the net length, and the metal layer in which the net is routed, a separate discussion for a separate post! :)); increase the launch clock path delay by X% and decrease the capture clock path delay by X%. Here you might want to check the post on Common Path Pessimism to see what type of clock path cells need to be exempted from OCVs.
Setup Analysis under OCV
  • Hold Analysis under OCV: Hold check would be the exact opposite of what we did for setup, namely decrease the data path delay by X% (you can take a call whether or not to apply a derate on the net delays. Usually, we don't apply derate on net delays); decrease the launch clock path delay by X% and increase the capture clock path delay by X%.
Hold Analysis under OCV

We talked so much about spatial correlation, then inherent cancellation of random variations but didn't use either of these concepts while explaining OCVs. This is the precise reason OCVs tend to be generally pessimistic. And as we shrink the technology node, a need arises for an intelligent methodology to perform variation aware timing analysis. And the answer is AOCV.

Let's take a look at AOCV in detail:

Advanced On-Chip Variations (AOCV): AOCV methodology hinges on three major concepts:
  • Cell Type: Variations should take into account the cell-type. Surely an AND gate an an OR gate can't exhibit the same variation pattern. Nor could an AND3X and an AND6X cell. The impact of variation should be calculated for each individual cell.
  • Distance: As the distance in x-y coordinates increase, the systematic variations would increase and we might need to use a higher derate value to reflect the uncertainty in timing analysis to mitigate any surprises on silicon.
  • Path Depth: If within a given distance, path depth is more, the impact of systematic variations would be constant, but the random variations would tend to cancel each other. Therefore as the path depth increases (within the same unit distance), the AOCV derates tend to decrease.
Bounding Box Creation for AOCV

While performing reg2reg timing analysis, AOCV methodology finds the bounding box containing the sequentials, clock buffers between two sequentials and all the data cells. Now within a unit distance, if the path depth increases, the AOCV derate decreases due to cancelling of random variations. However, if the distance increases, AOCV derates increases due to increase in the systematic variations. These variations are modeled in form of a LUT.

Sample AOCV Table for Setup Analysis

Now some final comments for OCV vs AOCV. 

  • For small path depths, OCV tends to be more optimistic than AOCV. (AOCV is more accurate).
  • For higher path depths, OCV tends to be more pessimistic than AOCV. (AOCV is still more accurate).
I hope you were able to draw the above inference. If not, I'd be willing to engage in discussion down in the comments section. See you all till next time! :)


  1. Aniket PatwardhanMarch 01, 2017 11:30 PM

    This is a nice article on this concept.. would just like the add couple of things .. these variations are also dependent on the voltage and so are quite often modelled with different factors depending on the corner used for analysis .. eg. Even if the variation is the same, at high vcc it's impact would be more pronounced where delays reduce .. so this is taken into account and you gaurd band ur timing window accordingly as a way of taxing for these variations ..

    1. Thanks for your comment, Aniket bhai.
      I beg to differ here. I believe the impact of variations should be more pronounced when vcc is low. That would be because any subtle or minor variations in the transistor threshold voltage would impact the delay more because the operating voltage was less. Had the operating voltage been high (as in upper nodes like the 90nm+), the small variations in the Vt would not have become more pronounced.
      Quantitatively, I agree, *if variatoon had been the same* when vcc is high, delays are less, therefore any variations (that would manifest as a delta delay) would be more pronounced. But I believe, at higher voltage, the variation itself would be less.
      I agree that while developing AOCV tables, one needs to take into account all the P, V and T because the derate factor would certainly depend on these parameters.
      Kindly share your thoughts! :)


    2. Small query over vt change. It's function of temperature and other process parameters , it's impact on timing is considered using low temp characterized ibraries. Can you please tell me what in general impacts the vt here.

  2. Hi Naman,

    I would like to know why do random variations tend to cancel out as the path depth increases ?


    1. Hi Santosh,
      That's the inherent nature of random variations and it's not just limited to the realm of semiconductor physics, but transcends into quantum mechanics, and entropy in thermodynamics as well. I fear I don't have the insight of a process engineer and I won't be able to explain it any better. Kindly let me know if you come across an explanation that would make sense to us engineers! :)

      Thanks again!

    2. Thanks for your reply, Naman. I would post it here when I find out :)

      Further, what is the difference between path depth and the distance. If distance is measured as a unit distance, how is path depth quantified ?


    3. Depth is quantified by the number of logic stages (number of logic gates) within the same distance.

  3. Great post! Loved your post!!

    Can you write a post on filler cells and their use?

  4. Excellent post and detailed explanation .
    Also please post the difference between AOCV and POCV, if Possible.


  5. Good post. I am still having confusion regarding path depth and distance. Can you explain more in detail about what is path depth in this regard? Or provide some material link for same.

  6. Very Nice Post and gave lot of clarity!!
    Can you share POCV details as well. That will be really helpful.

  7. Hi Naman,

    Thank you for your excellent blogs !!
    My question is - How is the table for AOCV characterized? What parameters are taken into consideration or is it only the PVT's?

  8. Thanks for the Post.
    I would like to add. AOCV Table for hold analysis will have a different trend. Derate increase with depth for a given distance and derate decrease with distance for a given depth.


  9. "Random variations tend to cancel each other"
    Does this have to do something with 'Vt' change in complementary logic for a unit distance. Change in Vt might affect both rise and fall delays of gates. This is the only explanation I could come up with for cancellation of random variations. Can this be a valid reason?

  10. Hi, Nice article, but I thought that the Variations in the Threshold voltage of a transistor is due to manufacturing variations and not random variations right? Correct me if I am wrong, if that's the case then it should be systematic variation right ?