IR Drop Analysis

Just yesterday, I got a question from one of our readers Lakshman Yandapalli. I thought it would be nice to write a blog post for you all!

Let's start with some background as to what indeed is the IR drop analysis.

When we talk about standard cells, we usually talk about the logical pins, let's say, A and B for the inputs and Z for outputs. What we do miss stating explicitly are the power/ground pins: the VDD and the VSS. These connections are usually implicit from the context (unless of course if you have a Muti-voltage design! Let's save this story for some other post).

IR drop is the voltage drop in the metal wires consituting the power grid before it reaches the VDD pins of the standard cells. Why do we bother about the voltage? Because the speed of the standard cell (the propagation delay) would be directly proportional to the VDD value. Higher VDD would mean faster cell, or lower propagation delay.

Now imagine that your SoC has a nominal voltage of 1V, and you closed your setup timing assuming the ideal 1V libraries. However, the IR drop of 40mV came into picture after you built the power grid, and the voltage is no longer 1V, let's say it is 0.96V. Now, with V = 0.96V, the delays of standard cells would be higher and you might see an increase in your setup-time violations!

Let's look into the factors that could cause this IR drop and how can we mitigate those factors, and what should our sign-off corners be to make sure no failures post-silicon!

While considering IR drop, you'd be concerned with two factors:

1. Static IR Drop: Dependent on the RC of the power grid connecting the power supply to the respective standard cells.

It is ALWAYS desirable to create the POWER GRID in higher metal layers. Higher metal layers would mean more wide wires, and hence would mean lower resistance. Lower resistance would mean that the IR drop would be lower, and hence lesser impact on setup-timing. 

Capacitance of metal wires would be the combination of ground and the coupling capacitance. If for some reason, you feel that the capacitance is too large, and it is indeed the reason for IR drop, it could either be because 

• Long wire length: Resulting in higher wire cap. 
• High fan-out of the net: Resulting in higher load-cap, or perhaps 
• High routing congestion in a particular area resulting in high coupling capacitance with the neighboring nets.

Now, how to mitigate the problem? You can try splitting the net so that the fan-out gets distributed (pretty much similar to building a clock tree), you can split the long wire by placing appropriate power bumps. Or you can also analyze the congestion and space the wires apart to reduce coupling capacitance!

Update: 

Simple equation representing the static IR drop would be the following:

Vstatic_drop = Iavg x Rwire

2. Dynamic IR Drop: Dependent on the switching activity of the standard cells themselves.
Switching activity of standard cells also contributes significantly to the IR drop, also known as the Dynamic IR drop. Higher would be the switching activity, in a given region, there'll be an increased demand for current from the power supply. More is the current, more would be the IR drop (which is essentially Current times the wore resistance!).
If you ever come across such a use case, you might want to space the standard cells apart so that the burden on a given bump to feed many standard cells which have high switching activity would be mitigated. 
Dynamic IR Drop is also sometimes referred to by the term of Voltage "Droop".
Update: Dynamic IR drop is contingent upon the current drawn by the standard cells, and that brings in a time-dependent variation of current into picture. Dynamic IR drop is represented by the equation:

Vdynamic_drop = L (di/dt)

Now that we have a fair understanding of IR Drop analysis, let's talk about the PVT/RC corners where one should analysis IR drop in their design.

Let's start with the RC corner.

1. RC Corner: The RC corner where the physical design engineers should analyze for IR drop would be the case when the RC product is worst. And that would indeed be the (RC)max corner, also referred to as the RCWorst corner.

2. PVT Conditions: PVT conditions would typically impact the standard cells. For IR drop analysis we would be concerned about the case where we expect the highest switching activity for standard cells. That would be the FF corner, High voltage, and high temperature.

High temperature might seem an anomaly, but higher temperature would mean higher wire resistance as well, and hence higher RC!

Last comment about IR drop analysis. It also makes sense to run IR drop analysis for the worst case setup timing check because IR drop would most probably impact only setup timing. So, designers may want to run the IR drop analysis for the RCWorst, High Temperature, SS slow and low voltage. But typically it is not done because the low voltage corner is usually already guard-banded to account for the IR drop. So, running IR drop analysis on the low voltage corner would be overly pessimistic!