September 18, 2016

Register Banking

Register Banking, also referred to as Multi-Bit Register Banking is a physical implementation technique of merging two or more flip-flops into a single multi-bit register. Let's first look at what all flip-flops are potential candidates for implementing register banks.

Technically speaking, any two flip-flops which share the same clock, the same asynchronous control pins, e.g. the reset or the preset pins, and the same scan enable pins are potential candidates for register banking. Before we delve any further, let's talk about the incentives for designers to use register banking for their design? 

Advantages of register banking:

  • Illustrating with the example of 2-bit register banks, one can easily see that the overall pin density of the 2-bit MBFF has significantly reduced as compared to using 2 standalone flip-flops. By pin density, I refer to the number of pins per unit area of silicon. While, the number of pin per standard cell has certainly increased, the overall pin density would be less. Higher pin density is the major cause of shorts in the SoCs. Reducing the pin density can therefore not only mitigate the short count, but also reduce the DRC count post-routing. 

    By sharing the scan enable, clock pin, reset pin, and the scan input pin one can reduce the total pins from 12 to 7 just by using a 2-bit register bank. Imagine the benefits when one would go for higher order register banks! I have used up to 8 bit register banks and now I can appreciate the reasons better! :)
  • While reducing pin density is indirectly useful, there's more tangible gain. That is the area! Circuit designers can do a better optimization of transistors when they have to fit two flip-flops on a single standard cell versus when designers have to use 2 standalone flip-flops. Hence, the overall area of a MBFF (Multi-bit FF) will always be more optimum.

  • Third advantage would be the optimum use of routing resources. Imagine routing signals like Scan Enable, Reset and Clock to 8 sequentials instead of one! However, the benefits won't scale by the same ratio of 8:1, using a MBFF would use lesser routing resources over using standalone FFs.

  • The biggest and the foremost reason behind using register banking is something different. I'm sure you must have guessed it by now. And it is the dynamic power! If you have lesser number of clock sinks, that would mean you need to route the clock to fewer sequentials. This would directly translate into using lesser number of clock buffers, hence lesser DYNAMIC POWER! This indeed is the motivation behind using register banking. Moreover, for FINFETs, owing to their 3-dimensional structure, the pin capacitance is significantly higher than their CMOS counterparts. Higher capacitance would directly mean higher dynamic power dissipation. Using register banking technique helps to offset some of that extra pin capacitance and reduces the overall dynamic power.
  • Ancillary benefits of register banking could be the requirement of lesser number of hold buffers or even reduction in the length of scan chain.

The biggest headache of using register banking technique is the Logic Equivalence Checks because mapping of the register banks to appropriate sequentials from the RTL becomes quite difficult. LEC, among many things, checks for the name of the sequentials while mapping and checking the equivalence between the golden and the revised sides. The instance name of the register bank is usually a combination of the instance names of all the standalone flip-flops comprising the multi-bit register. Hence LEC may have a tough time in establishing the equivalencies. 

While theoretically, register banking sounds simple, the designers or alternatively the design tools should exercise care in choosing the standalone sequentials for register banking. In addition to ensuring that the scan enable, clock signal and the asynchronous control signals are same, it is also desired that the length of the combinational cloud feeding the individual data pins of the multi-bit flops be almost the same. If let's say, one input has a higher combinational depth as compared to other inputs, the clock to the multi-bit sequential might need to be "pushed" to meet timing, and thereby offsetting the benefits of register banking. Excess use of clock buffers might even lead to congestion issues and would significantly eat up the routing resources.


  1. Hey! Thanks Naman,

    I have one quarry "How tool will give priority to choose a group of Registers as a MB reg ?"

    like: based on clock sinks? based on Startpoint & Endpoint ? or based on setup/hold timing optimization requirement ? or based on placement of regs ?

    It will be good if someone explain this in depth,

    Nilesh Ramani

  2. It will check for common clock, ICG, SI and SE first, if they are common then you can specify in tool to do timing driven, location driven clustering/converting.