August 17, 2012

Clock Gating Integrated Cell

In the post, Clock Gating, we discussed the need for Clock Gating for Low Power Design Implementation. Clock being the highest frequency toggling signal contributes maximum towards the dynamic power consumption in the SoC even when the flops that are being fed by the clock are not changing their state. So, it is practical to gate the clock from reaching the set of registers or maybe some block in a design to save on the dynamic power consumption.

 You can relate it to the Standy mode in your PCs. In standy mode, only a sub-system of your entire SoC is working. Hence to save on the power consumption, one can employ clock gating. (Or maybe some other power saving methods, that we will discuss later).

Instead of using an AND or an OR gate for clock gating which is vulnerable to glitchy output, design engineers prefer to use the Clock Gating Integrated Cell (CGIC) to completely obviate the problem. Here's the circuit of a CGIC:

As evident from the above waveforms, if enable EN of the CGIC is logic-1, CGIC passes on the clock at the output without any glitch. And if EN is at logic-0, the outpiut is gated, i.e. no clock at the output and hence saving on the dynamic power consumption in the device.


  1. shouldnt it be a negative edge triggered flip flop than a latch?

    if the enable were to change from 1->0 or 0->1 in the low period of the clock, wouldnt it still result in the glitch at the output?

    1. No as AND gate is used. Negative edge of clock will not be traversed to gated clock. Only at positive level of the clock will result in output following latch output

  2. During low period of clock, AND gate ensures output is low. Once latch closes at end of low period, state of enable at that time is preserved to ensure clock is not clipped or glitched by enable state change.

  3. There is 2 min path( one to latch, one to and), 1 half cycle max path( latch to and) in the circuit, as long as those 3 paths have no timing violation, the circuit works fine. Only thing is the EN pin has large setup time( latch d2q delay) wrt clk. It is shown in the timing diagram above

  4. The AND gate is low-inactive, so the enable can change only during clock is low. There are questions and answers about this in book "Physical Design Interview Questions" from Amazon.

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