Puzzle: Stuck-at Fault

Around 2.5 years back, I had posted a Puzzle: Stuck-At Fault on this blog where I had asked to find the input vector to detect a particular stuck-at fault in a given circuit. This puzzle is exactly the same problem, but with a more complex circuit.

Assuming a SINGLE STUCK-AT FAULT MODEL, could you please help me with the input vector to detect:

1. A Stuck-at-0 fault at node L.
2. A Stuck-at-1 fault at node L.

Please post your answers in the comment section below.

Channel Length vs Gate Length

Till a few months back, I assumed that channel length and gate length were same terms used interchangeably. However, one of the classes that I took at USC cleared this doubt and I'm very thankful to my professor for explaining the subtle difference between the two.

The figure above shows the cross-section of an NMOS with it's source, drain, gate. Let's talk about the difference between gate length, channel length and the diffusion length.

While fabricating a MOS device, typically the poly gate is grown first using the minimum feature size mask which is characteristic of a particular technology node. After this, the source and drain are formed by ion-implantation of Phosphorus (n+). This is referred to as self-aligned process. After ion-implantation, there is some side diffusion of the implanted ions because of which, the n+ region extends up to a small width below the gate. This is referred to as the diffusion length or the diffusion width. The effective distance between the drain and the source where the channel would eventually be formed and the actual length an electron would travel from source to drain is called the Effective Channel Length! I encourage you to read up more about the steps in CMOS Fabrication for better understanding. 

As evident from the above figure:

Channel Length = Gate Length - 2 x (Diffusion Length)

Well, that was theory! Now some practical discussion. :)

When we say that we have let's say a 28 nm technology node. Which of the above would be 28 nm? Well, it would be the GATE LENGTH! As pointed above, gate corresponds to the minimum feature size mask which is characteristic of a particular technology node!

Now, let's say, this NMOS is operating in the saturation regime, and there's no pinch off yet. If you wish to find the saturation current flowing through the device, you'll have to use the channel length in the formula for the drain current which is a quadratic function of the gate-to-source voltage. 

How do we find this channel length? For older technology nodes (like 250 nm), this diffusion used to be negligible as compared to the gate length. However, for advanced sub-micron technology nodes, the side diffusion length is typically 10% of the gate length. (Actual numbers may vary from one manufacturer to another). So, for 28 nm technology node, you might expect the actual channel length to be in the order of 20-22 nm.

Drain and the Source of MOS Transistors

How does one decide which terminal of the MOS Transistor is the Source and which terminal is the Drain?

While most of us are taught one basic rule in our introduction classes to the CMOS Transistor: The source of an NMOS is typically at the lowest potential while the source of a PMOS transistor is at the highest potential. 

While this rule is correct, there got to be a plausible technical explanation behind this nomenclature. In this post, I'll discuss that explanation.

First of all one must appreciate the fact that unlike BJT, MOSFET is a symmetric structure. By this, I mean that any terminal can act as drain or source depending upon the voltage applied on that particular terminal. In NMOS: Source is the terminal which is at the lowest potential. In PMOS, Source is the terminal with the highest potential. Now, the question arrives why did we choose to call a particular terminal as source or drain. Read on.

In NMOS, the majority charge carriers are the electrons. If you've followed the physics behind the transistor operation, you'd know that current in an NMOS flows from Drain to Source. Alternatively, electrons flow from the source to drain. Source is therefore the "reservoir" or "source" of electrons which get "drained" at the Drain! That's where the terminology comes from. Therefore, the source of electrons in an NMOS has to be connected to the lowest potential, that being the VSS. And Drain to the higher potential, which could perhaps be VDD.

In PMOS, the majority charge carriers are the holes. Holes will flow from higher potential to a lower potential. Higher potential terminal would act as the "source" of holes. That would therefore be VDD. These holes would get "drained" at a lower potential, which could perhaps be VSS. Therefore, for PMOS, higher potential terminal would be the Source, and lower potential terminal would be the drain! 

The Timing Optimization Problem

Puzzle:

Tomorrow is the scheduled tape-out of your SoC. The target clock frequency for this SoC is 100 MHz (Time Period of 10 ns). However, there's only one setup violating path and you need to fix the timing by doing ECOs. Area is not a constraint.

Here's the circuit:

Points to note:

• My tape-out is tomorrow, I don't have the liberty of asking the RTL design team to change the architecture of the design.
• I have used the highest possible drive strength cells, and perhaps the lowest Vt flavor cells available in my standard cell library.
• There's no redundant logic in the path, it's been optimized well.
• I cannot add delay to the clock path of FF2 because doing so, the hold time of the scan chain connecting flops FF1 and FF2 would fail.

Please suggest ways to solve this timing violation. A rough image would be really helpful. I shall post my solution in a couple of days time.

Mike posted the correct answer, and I'll just add a figure explaining the solution:

Puzzle: Vt Flavors of Standard Cells

Let's say you have the following flavors of standard cells (say NAND):

• NAND2_HVT_X2 (A two-input NAND gate, of High-Vt and drive strength 2).
• NAND2_HVT_X4
• NAND2_HVT_X8
• NAND2_LVT_X2
• NAND2_LVT_X4
• NAND2_LVT_X8

Can you help me arrange these cells in the decreasing order of their:

• Area
• Delay
• Leakage Power

Also please answer the following:

• Which cell(s) are you more likely to use on a setup-critical path?
• Which cell(s) are you more likely to use on a hold-critical path?
• Which cell(s) are you more likely to use in a chip with stringent low standby power specifications?

And the last question: which among the following do you think is responsible for different threshold voltage (Vt) characteristics of HVT and LVT cells:

1. Different doping profiles of HVT and LVT cells.
2. Different gate lengths of HVT and LVT cells. (Also called Gate Length Biasing).
3. Both of the above.
4. None of the above.

Hint: At some places, few quantities might be equal, so make sure you use equality instead of greater than.

Please post your answers in the comments below.

IDDQ Testing

IDDQ is the IEEE symbol for Direct Drain Quiescent Current and IDDQ Testing measures this current to discriminate between a good and a defective chip. But how could current be used to detect a fault? Read on!

IDDQ testing is gaining popularity among DFX (DFT, DFV, DFM etc condensed into DFX) engineers because it's cost effective and can detect faults which might be left undetected by traditional DFT techniques like the scan testing (stuck-at fault testing), atspeed testing (transition fault testing) or delay testing. IDDQ testing helps ascertain an extra degree of confidence that the manufactured chip is defect free and hence the defect level (the number of defective chips per million manufactured chips shipped to the customer) is low.

Principle: IDDQ testing is based on the principle that complimentary CMOS does not draw any current from the power supply when it's inputs are static (i.e. not switching). In reality, however, there exists a small leakage current which typically is orders of magnitude smaller than the switching current. By this definition, all CMOS circuits are 100% IDDQ testable. 

Faults detected by IDDQ tests:

• Bridging Faults: Shorts between two nodes causing a voltage contention because they are being driven by two conflicting voltages. Sometimes also referred to as stuck-on faults.
• Punch-through: Short between Drain and the source.
• Resistive Shorts
• Line and Gate Break Faults
• Source or Drain Break Faults
• Even some Delay Faults
• Latch-Up
• Stuck-open Faults,

Examples:

• Bridging Fault: If there exists a short (which could perhaps be because of some extra metal caused by process variations) between two wires which are driving opposite logic values, the voltage at the node might be at any intermediate level between VDD and 0. In the worst case it could be stuck at VDD/2, causing metastability at the flip-flop and hence a functional failure. If the two inverters in the circuit below are driven to opposite values, there's a current flow from the power supply of one inverter to the ground of another which would be typically in the range of tens of micro-amps (as opposed to nano-amps leakage current). This anomaly can be detected by IDDQ testing.

• Line Break Fault: If the input to any gate is broken (possibly because of mask misalignment), the input becomes floating. This floating input might attain any value which in the worst case might result in conduction through both NMOS and PMOS transistors, thereby resulting in a large current flow through the device.

The principle behind stuck-on faults, gate, drain and source break fault is fundamentally similar to the line break fault. 

Gate, drain and source break faults manifest inside the standard cells where there exists an open at either one or more of the transistor terminals, again causing a floating node and hence an unknown voltage value resulting in high current!

Refer to the post on Latch-Up to understand how does Latch-Up result in a high-current flow through the CMOS device. This high current flowing through the device can be propagated to the power rail and detected using IDDQ test vectors.

Caveat of IDDQ Testing: 

• There might exist a few corner cases where a good circuit might be identified as a faulty by IDDQ testing. Such cases can be reverse-engineered to ascertain to be false, however, it might take a lot of effort and debug-time. Discussing such cases is beyond the scope of this blog post.
• As mentioned earlier, IDDQ testing can be used for CMOS circuits. Dynamic Logic has been gaining a lot of attention in the recent years in high-speed applications. Dynamic Logic circuits cannot be tested using IDDQ testing because it exhibits precharge property where the output capacitance is charged every time in the precharge phase irrespective of the value at inputs (even if they are static!)

Comparison with other testing methodologies:

• While other testing methodologies like scan and atspeed rely on detecting the voltage level at the node in question which is being tested for a desired fault, IDDQ testing senses current levels. 
• Traditional testing methodologies rely on the two pillars of DFT namely: controlability and observability as the sensitized fault (controlability) needs to be propagated to the output (observability), in order to detect a fault. In IDDQ testing, all faults are propagated to the power supply which is much easier to do so. Hence, typically, only 2-3 test vectors are sufficient to achieve a 50% fault coverage for IDDQ testing.
• Scan and atspeed testing require ATE (Automatic Test Equipment) to apply test patterns and receive the output of the DUT (Device Under Test). IDDQ tests require an off-chip current monitoring device, in addition to the ATE.

References: 

• IDDQ Made Easy. CMOS IDDQ Test Methodology by Bob Duell, Systems Science Inc.
• IDDQ Testing Outline. Lecture Slides by Dr. Wenben Jone, University of Cincinnati.

Puzzle: Wire Delay

Technical Tidbit:

You have a long wire of let's say length L. And it has the net delay of 100ps. Now you split the wire into two equal halves of length 0.5L each and insert a buffer at the center of the wire. The delay of buffer is 25ps. What is the total delay of the system: (half wire+ buffer + half wire)?

Option a: 50+25+50= 125ps
Option b: 25+25+25=75ps
Option c: 25+25+50=100ps
Option d: 50+25+25=100ps

Choose the right option, and please give a short explanation.

Thanks!

Puzzle: Best Performing Processor

You have 3 different processors:

• Single Cycle CPU
• Multi Cycle CPU
• Pipelined CPU

All the three processors, somehow magically, are clocked at the same rate. Can you arrange these processors in the descending order of the performance and a small explanation for the answer?