OCV v/s AOCV

When I had started my career around 6 years back, we were introduced to the term called OCV. While the OCV concept was quite simple and fascinating, it didn't me long to realize that OCV can be a nightmare for every STA engineer out there. I had introduced OCV long time back while explaining the difference between OCV v/s PVT. In this post, I intend to draw a distinction between OCV (On-Chip Variation) and AOCV (Advanced On Chip Variation).

Before we discuss anything about OCVs, it would be prudent to talk about the sources and types of variations that any semiconductor chip may exhibit.

The semiconductor device manufacturing process exhibit two major types of variations:

• Systematic Variations: As the name suggests, systematic variations are deterministic in nature, and these can usually be attributed to a particular manufacturing process parameter like the manufacturing equipment used, or perhaps even the manufacturing technique used. Systematic variations can be experimentally calibrated and modeled. They also exhibit spatial correlation- meaning two transistors close to each other would exhibit similar systematic variation- which makes them easier to gauge. Example would be inter-chip process variations between two different batch of manufactured chips.
  When a certain technology is in its nascent stage (let's say 10-nm technology), the process engineers would typically be more concerned about these variations and as the technology matures, process engineers are able to calibrate and tune their manufacturing process to reduce this variation component.
• Random Variations: These are totally random, and therefore non-deterministic in nature. Random variations do not show spatial correlation and therefore very difficult to gauge and predict. Unlike systematic variations, random variations usually have a cancelling effect owing to their random nature. Examples are subtle variations in transistor threshold voltage.

As the semiconductor node shrinks, the susceptibility to the variations increase. And the effect of these variations need to be taken into account while doing timing analysis, or perhaps during the overall design planning to some extent. Shifting our focus back to OCV and AOCV. At this time one may ask themselves in what form would these variations manifest themselves? Well, these variations can manifest themselves in form of increase or decrease in the threshold voltage of devices, shift the process of the manufactured devices, perhaps vary the oxide thickness or change the doping concentration..

There might be infinite such manifestations and we engineers like to make our lives easier, don't we? ;)

Experienced folks must have guessed where am I headed. If you haven't guessed it yet, stay with me, take a step back and what does all these parameters have in common? What's that one quantifiable metric that these will impact and the answer is the delay! OCV and AOCV are essentially models which guide us on how the cell delay varies in light of the systematic and random variations.

On-Chip-Variations (OCV): OCVs are simplistic and (generally) pessimistic view of modelling process variations. Here we use that the delay of all cells can show, let's say X% variation in their delays. Now you would either model this variation as -X% to +X%, or perhaps -(X/2)% to +(X/2)%. Let's say we choose the latter. Now we would model the delay of all cells and subject them to OCVs in a manner that our timing becomes pessimistic and we can claim that in the worst case, as long as process guys can ensure that the variation would be within the bracket of -X% to +X%, we'd be safe.

• Setup Analysis under OCV: In order to make setup analysis immune to process variations on silicon, we need to model the OCVs such that setup check becomes more pessimistic. That would be the case if we increase the data path delay by X% (you can take a call whether or not to apply a derate on the net delays. One can choose to apply a net derate based on the net length, and the metal layer in which the net is routed, a separate discussion for a separate post! :)); increase the launch clock path delay by X% and decrease the capture clock path delay by X%. Here you might want to check the post on Common Path Pessimism to see what type of clock path cells need to be exempted from OCVs.

Setup Analysis under OCV

• Hold Analysis under OCV: Hold check would be the exact opposite of what we did for setup, namely decrease the data path delay by X% (you can take a call whether or not to apply a derate on the net delays. Usually, we don't apply derate on net delays); decrease the launch clock path delay by X% and increase the capture clock path delay by X%.

Hold Analysis under OCV

We talked so much about spatial correlation, then inherent cancellation of random variations but didn't use either of these concepts while explaining OCVs. This is the precise reason OCVs tend to be generally pessimistic. And as we shrink the technology node, a need arises for an intelligent methodology to perform variation aware timing analysis. And the answer is AOCV.

Let's take a look at AOCV in detail:

Advanced On-Chip Variations (AOCV): AOCV methodology hinges on three major concepts:

• Cell Type: Variations should take into account the cell-type. Surely an AND gate an an OR gate can't exhibit the same variation pattern. Nor could an AND3X and an AND6X cell. The impact of variation should be calculated for each individual cell.
• Distance: As the distance in x-y coordinates increase, the systematic variations would increase and we might need to use a higher derate value to reflect the uncertainty in timing analysis to mitigate any surprises on silicon.
• Path Depth: If within a given distance, path depth is more, the impact of systematic variations would be constant, but the random variations would tend to cancel each other. Therefore as the path depth increases (within the same unit distance), the AOCV derates tend to decrease.

Bounding Box Creation for AOCV

While performing reg2reg timing analysis, AOCV methodology finds the bounding box containing the sequentials, clock buffers between two sequentials and all the data cells. Now within a unit distance, if the path depth increases, the AOCV derate decreases due to cancelling of random variations. However, if the distance increases, AOCV derates increases due to increase in the systematic variations. These variations are modeled in form of a LUT.

Sample AOCV Table for Setup Analysis

Now some final comments for OCV vs AOCV. 

• For small path depths, OCV tends to be more optimistic than AOCV. (AOCV is more accurate).
• For higher path depths, OCV tends to be more pessimistic than AOCV. (AOCV is still more accurate).

I hope you were able to draw the above inference. If not, I'd be willing to engage in discussion down in the comments section. See you all till next time! :)

Small Delay Defect Testing

Small Delay Defect Testing is an important step in ATPG testing towards realizing the strategic goal of zero DPPM (Defective Parts Per Million). 

What is SDD? And why is it needed?  

With shrinking technology nodes, the silicon is becoming increasingly susceptible to manufacturing defects like- stuck-at faults, transition faults etc. Variations in PVTs and OCVs make the silicon even more vulnerable to failure. While in Stuck-at capture, we test the device for manufacturing defects like- shorts and open; in At-Speed testing the device is tested for transition faults at the functional frequency. 

Small Delays are any subtle variations in the delay of standard cells due to OCVs. These small delays (when accumulated) have the potential to fail the timing of the critical paths at the rated frequency. The testing mechanism deployed to test the faults arising due to these small delays is referred to as Small Delay Defect testing. 

Sounds more like ATPG-Atspeed, right? Then, where lies the difference? The difference lies in the intent. While At-Speed Testing, the intent of DFT is to target fault simulation for each node by hook or by crook! With the focus of modern ATPG tools being on pattern reduction and hence the test time, it tries to target each node via the most convenient path, which is typically the shortest path.

Consider the below use-case. 

Path 3 is the shortest path to target the node X. ATPG-Atspeed would take Path 3 to generate the patterns in order to test node X. As evident from above, Path 1 is the most timing critical path and therefore is more probable to violate timing on silicon. SDD targets such paths!

I have one question. And would request the readers to pour-in their view regarding it:

• Small Delay Defect is traditionally done for setup-violations. But let's say, in case of significant clock skew between any two interacting flops, even hold timing would be critical. Can one possibly use something similar to target hold violations due to small delay as well?

Reference:

1. ​​'Small Delay Defect Testing' by Roberto Mattiuzzo. Published at EDN, June 2009. 

OCV vs PVT

In the post PVTs and How They Impact Timing, we talked about the confluence of the Process-Voltage and Temperature factors and their impact on timing. I would urge the readers to go through the post in order to grasp the difference between two key terminologies used in the VLSI industry- 

• OCV: On Chip Variation;
• PVT: Process, Voltage and Temperature

While PVTs are inter-chip variation which depend largely on external factors like: the ambient temperature; the supply voltage and the process of that particular chip at the time of manufacturing. Like PVTs, OCVs are also variations in process, voltage and temperature. But, hey, where's the difference? OCVs are intra-chip variations! To elucidate more about the OCVs, let's talk in terms of chips!

• Variation in Process: There are millions of devices (standard cells); and probably billions of transistors packed on the same chip. You can expect every single transistor to have the same process or the channel length! If we say that the chip manufactured exhibits, let's say, worst process, it means that the  channel length tends to deviate towards the higher side. This variation may be more for some transistors and less for some. It can be a ponderous task to quantify this variation between the transistors of the device, and is often modeled as a percentage deviation from the normal.
• Variation in Voltage: All the standard cells need voltage supply for their operation. And voltage is usually 'tapped' from the voltage rail via interconnects which have a finite resistance. 

In two parts of the chip, it is fairly probable for the interconnect length to be different, resulting in a finite difference in the resistance values and hence the voltage that the standard cells actually receive. As evident above, the voltage received by the standard cells on the right would be less as compared to those on the left.

This variation would be less, probably of the order of a few mili-volts, but is can be significant, is again modeled as OCV.

• Variation in Temperature: Some parts of the chip can be more densely packed or might exhibit more active switching ss compared to the other parts. In these regions, there is a high probability of the formation of localized 'HOT SPOTS' which would result in increased temperature in some localized areas of the chip. Again, this difference might be order of a few degree centigrade, but can be significant.

All the above mentioned variations are examples of On-Chip-Variations. And usually, these variations are modeled as a fixed percentage of delays. For examples, a 4% OCV derate would mean, that the delays of cells in the data path are inflated by 4% while doing setup analysis and decreased by 4% while doing hold analysis. Same methodology is applied for the clock paths. However, it would be different for launching and capture clock paths. That also gives rise to an interesting topic of Common Path Pessimism Removal which we shall take up shortly. 

PVTs and How They Impact Timing

PVT is acronym for Process-Voltage-Temperature.

PVTs model variations in Process, Voltage and Temperature. There's other term OCV which refers to On-Chip Variation. PVTs model inter-chip variations while OCVs model intra-chip variations. 

We'll talk about OCVs in some other post.

Let's talk about PVTs in detail:

1) Process: You must have heard people talking in terms of process values like 90nm, 65nm, 45nm and other technology nodes. These values are characteristic of any technology and represents the length between the Source and Drain of a MOS transistor that you might have studied in your under-grad courses. While manufacturing any die, it has been seen that the dies that are present at the center are pretty accurate in their process values. But the ones lying on the periphery tend to deviate from this process value. The deviation is not big, but can have significant impact on timing.

Recall from your undergrad courses the following formula for current flowing in a MOS transistor:

                                             

L represents the process value. For same temperature and voltage values, current for 45nm process would be more than current for 65nm process.

More is the current, faster is the charging/discharging of capacitors. And this means, delays are less.

2) Voltage: The voltage that any semiconductor chip works upon is given from outside. Recall while working on breadboards in your labs, you used to connect a 5V supply to the Vcc pin of your IC. Modern chips work on very less voltage than that. Typically around 1V-1.2V.

This voltage must be the output of either a DC source or maybe the output of some voltage regulator. The output voltage of voltage regulator might not be a constant over a period of time. Let's say, you expected your voltage regulator to give 1.2V, but after 4 years, it's voltage dropped down to 1.08V or increased up to 1.32V. So, you gotta make sure your chip is working well between 1.08 and 1.32V!!

This is where the need to model Voltage variations come into picture.

From the same equation as above, it can be seen that more is the voltage, more is the current. And hence, delays are less.

3) Temperature: The ambient temperature also impacts the timing. Let's say you are working on a gadget in Siachen glacier where temperature can drop down to -40 degrees centigrade in winters and you expect your device to be working fine. Or maybe you are in Sahara desert, where ambient temperature is +50 degrees and your car engine temperature is +150 degrees and again you expect your chip to working fine. While designing, therefore, STA engineers need to make sure that their chip will function correctly in the temperatures between -40 to +150 degrees.

Higher is the temperature, more is the collision rate of electrons within the device. This increased collision rate forbids other electrons in the periphery to move. Since electron movement is responsible for current flowing in the device, current would decrease with increase in temperature. Therefore, delays are normally more at higher temperatures.

For technology nodes below 65nm, there's a phenomenon called TEMPERATURE INVERSION, where delays tend to increase with decreasing temperature. We shall talk about the same later. Don't get confused with it here.

WORST PVT: Process worst-Voltage min- Temperature-max

BEST PVT:  Process best-Voltage max- Temperature-min

WORST COLD PVT: Process worst-Voltage min-Temperature min

BEST HOT: Process best-Voltage max-Temperature max

STA engineers are responsible for closing the timing ( i.e. setup and hold ) at all these PVT corners.

So, next time you hear an STA engineer cribbing about his timing status across multiple PVTs, please show him some empathy!

Some related topics that we would discuss in upcoming posts:
1) On-Chip Variations and how they differ from PVT.
2) Temperature Inversion.
3) Factors affecting delays of standard cells.

Stay tuned for updates.