July 23, 2014

Small Delay Defect Testing

Small Delay Defect Testing is an important step in ATPG testing towards realizing the strategic goal of zero DPPM (Defective Parts Per Million). 

What is SDD? And why is it needed?  
With shrinking technology nodes, the silicon is becoming increasingly susceptible to manufacturing defects like- stuck-at faults, transition faults etc. Variations in PVTs and OCVs make the silicon even more vulnerable to failure. While in Stuck-at capture, we test the device for manufacturing defects like- shorts and open; in At-Speed testing the device is tested for transition faults at the functional frequency. 

Small Delays are any subtle variations in the delay of standard cells due to OCVs. These small delays (when accumulated) have the potential to fail the timing of the critical paths at the rated frequency. The testing mechanism deployed to test the faults arising due to these small delays is referred to as Small Delay Defect testing. 

Sounds more like ATPG-Atspeed, right? Then, where lies the difference? The difference lies in the intent. While At-Speed Testing, the intent of DFT is to target fault simulation for each node by hook or by crook! With the focus of modern ATPG tools being on pattern reduction and hence the test time, it tries to target each node via the most convenient path, which is typically the shortest path.

Consider the below use-case. 

Path 3 is the shortest path to target the node X. ATPG-Atspeed would take Path 3 to generate the patterns in order to test node X. As evident from above, Path 1 is the most timing critical path and therefore is more probable to violate timing on silicon. SDD targets such paths!

I have one question. And would request the readers to pour-in their view regarding it:
  • Small Delay Defect is traditionally done for setup-violations. But let's say, in case of significant clock skew between any two interacting flops, even hold timing would be critical. Can one possibly use something similar to target hold violations due to small delay as well?


  1. Hi Naman,

    Thanks for the article. You mentioned OCV defects in the second para. Can you please point me to some material on this defect? I couldn't find anything on Google.


    1. Hi Rahul. I didn't mean it as "OCV defects", but I meant it as variations arising due to On-Chip Variations. An STA engineer would perform timing analysis assuming a combination of PVT-RC corner. He might take into account some derates to account for the OCVs. But the actual scenario on silicon must transcend the modeled values and one might witness a timing failure.

      Please let me know in case of any query. You can find a lot of material on OCVs.


    2. Oh, that's okay then. Thanks!


  2. Nice article!
    But as hold is not dependent on frequency how can we possibly check for any violations ?


  3. what is the difference between path delay and small delay testing ?

  4. @ Naman..In the case of hold timing, We can insert a latch in a data path to make it more delayed than clock path.