VLSI SoC Design: Computer Architecture

VLSI SoC Design

VLSI SoC Design: Concepts, Perspective & Implementation

Pages

Home
About Me
Computer Architecture
DFT
Low Power Methodology
Physical Design
Puzzles
SoC Design
Tcl / Perl

Computer Architecture

Puzzle: Best Performing Processor

Email This BlogThis!Share to X Share to Facebook Share to Pinterest

1 comment:

AnonymousJune 19, 2025 8:23 PM
thanks for sharing
ReplyDelete
Replies

Subscribe to: Posts (Atom)

Pages

Home
About Me
Computer Architecture
Physical Design
Low Power Methodology
SoC Design
Puzzles
DFT
Tcl / Perl
Post Your Query

Blog Archive

▼ 2019 (1)
- ▼ June (1)
  - IR Drop Analysis - II

► 2018 (2)
- ► April (2)

► 2017 (4)
- ► April (1)
- ► March (2)
- ► February (1)

► 2016 (5)
- ► September (1)
- ► August (1)
- ► June (1)
- ► April (1)
- ► January (1)

► 2015 (8)
- ► December (3)
- ► November (1)
- ► September (2)
- ► January (2)

► 2014 (10)
- ► December (2)
- ► July (2)
- ► June (1)
- ► May (1)
- ► January (4)

► 2013 (27)
- ► August (1)
- ► July (2)
- ► June (3)
- ► May (2)
- ► April (5)
- ► March (8)
- ► February (3)
- ► January (3)

► 2012 (18)
- ► August (6)
- ► July (10)
- ► June (2)

Popular Posts

Inverter vs Buffer Based Clock Tree

A buffer is nothing but two inverters connected back to back. Does it make any difference if the CTS (Clock Tree Synthesis) is done using ...
PVTs and How They Impact Timing

PVT is acronym for Process-Voltage-Temperature . PVTs model variations in Process, Voltage and Temperature. There's other term O...
IR Drop Analysis

Just yesterday, I got a question from one of our readers Lakshman Yandapalli. I thought it would be nice to write a blog post for you al...
Clock Skew: Implication on Timing

Clock Skew is an important parameter that greatly influences the timing checks and you would often find the backend design engineers alway...
OCV v/s AOCV

When I had started my career around 6 years back, we were introduced to the term called OCV. While the OCV concept was quite simple and fa...
Timing Analysis: Graph Based v/s Path Based

Hello folks! In this post, I'm gonna talk about the difference between two commonly used Static Timing Analysis methodologies, namely-...
Power Domain Crossings

With all the fuss about low power designs, the implementation of multiple power domains has gained significant traction in the past decade...
Clock Gating Integrated Cell

In the post, Clock Gating , we discussed the need for Clock Gating for Low Power Design Implementation. Clock being the highest frequency ...
IR Drop Analysis - II

A couple of years back, I wrote about IR Drop Analysis in one of my earlier posts. Fortunately. I got to work on IR Drop Analysis more ext...
Clock Gating

Clock signal is the highest frequency toggling signal in any SoC. As we discussed in the post: Need for Low-Power Design Methodology , th...

.

Subscribe to the blog Facebook page

Followers

Labels

Basic Digital Electronics (3)
PVT (4)
Physical Design (8)
Puzzles (12)
Tcl (2)
Timing Arcs (1)

Total Pageviews

Subscribe To

Posts

Posts

All Comments

All Comments

Author

Naman
Unknown
Unknown

Simple theme. Theme images by enot-poloskun. Powered by Blogger.