VLSI SoC Design

VLSI SoC Design: Concepts, Perspective & Implementation

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      • IR Drop Analysis - II
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Popular Posts

  • Inverter vs Buffer Based Clock Tree
    A buffer is nothing but two inverters connected back to back. Does it make any difference if the CTS (Clock Tree Synthesis) is done using ...
  • PVTs and How They Impact Timing
    PVT is acronym for Process-Voltage-Temperature . PVTs model variations in Process, Voltage and Temperature. There's other term O...
  • IR Drop Analysis
    Just yesterday, I got a question from one of our readers Lakshman Yandapalli.  I thought it would be nice to write a blog post for you al...
  • Clock Skew: Implication on Timing
    Clock Skew is an important parameter that greatly influences the timing checks and you would often find the backend design engineers alway...
  • OCV v/s AOCV
    When I had started my career around 6 years back, we were introduced to the term called OCV. While the OCV concept was quite simple and fa...
  • Timing Analysis: Graph Based v/s Path Based
    Hello folks! In this post, I'm gonna talk about the difference between two commonly used Static Timing Analysis methodologies, namely-...
  • Power Domain Crossings
    With all the fuss about low power designs, the implementation of multiple power domains has gained significant traction in the past decade...
  • IR Drop Analysis - II
    A couple of years back, I wrote about IR Drop Analysis in one of my earlier posts. Fortunately. I got to work on IR Drop Analysis more ext...
  • Clock Gating Integrated Cell
    In the post, Clock Gating , we discussed the need for Clock Gating for Low Power Design Implementation. Clock being the highest frequency ...
  • Clock Gating
    Clock signal is the highest frequency toggling signal in any SoC. As we discussed in the post:  Need for Low-Power Design Methodology , th...

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