June 29, 2012

PVTs and How They Impact Timing

PVT is acronym for Process-Voltage-Temperature.

PVTs model variations in Process, Voltage and Temperature. There's other term OCV which refers to On-Chip Variation. PVTs model inter-chip variations while OCVs model intra-chip variations
We'll talk about OCVs in some other post.

Let's talk about PVTs in detail:

1) Process: You must have heard people talking in terms of process values like 90nm, 65nm, 45nm and other technology nodes. These values are characteristic of any technology and represents the length between the Source and Drain of a MOS transistor that you might have studied in your under-grad courses. While manufacturing any die, it has been seen that the dies that are present at the center are pretty accurate in their process values. But the ones lying on the periphery tend to deviate from this process value. The deviation is not big, but can have significant impact on timing.
Recall from your undergrad courses the following formula for current flowing in a MOS transistor:

L represents the process value. For same temperature and voltage values, current for 45nm process would be more than current for 65nm process.
More is the current, faster is the charging/discharging of capacitors. And this means, delays are less.

2) Voltage: The voltage that any semiconductor chip works upon is given from outside. Recall while working on breadboards in your labs, you used to connect a 5V supply to the Vcc pin of your IC. Modern chips work on very less voltage than that. Typically around 1V-1.2V.
This voltage must be the output of either a DC source or maybe the output of some voltage regulator. The output voltage of voltage regulator might not be a constant over a period of time. Let's say, you expected your voltage regulator to give 1.2V, but after 4 years, it's voltage dropped down to 1.08V or increased up to 1.32V. So, you gotta make sure your chip is working well between 1.08 and 1.32V!!
This is where the need to model Voltage variations come into picture.
From the same equation as above, it can be seen that more is the voltage, more is the current. And hence, delays are less.

3) Temperature: The ambient temperature also impacts the timing. Let's say you are working on a gadget in Siachen glacier where temperature can drop down to -40 degrees centigrade in winters and you expect your device to be working fine. Or maybe you are in Sahara desert, where ambient temperature is +50 degrees and your car engine temperature is +150 degrees and again you expect your chip to working fine. While designing, therefore, STA engineers need to make sure that their chip will function correctly in the temperatures between -40 to +150 degrees.

Higher is the temperature, more is the collision rate of electrons within the device. This increased collision rate forbids other electrons in the periphery to move. Since electron movement is responsible for current flowing in the device, current would decrease with increase in temperature. Therefore, delays are normally more at higher temperatures.

For technology nodes below 65nm, there's a phenomenon called TEMPERATURE INVERSION, where delays tend to increase with decreasing temperature. We shall talk about the same later. Don't get confused with it here.

WORST PVT: Process worst-Voltage min- Temperature-max
BEST PVT:  Process best-Voltage max- Temperature-min
WORST COLD PVT: Process worst-Voltage min-Temperature min
BEST HOT: Process best-Voltage max-Temperature max

STA engineers are responsible for closing the timing ( i.e. setup and hold ) at all these PVT corners.
So, next time you hear an STA engineer cribbing about his timing status across multiple PVTs, please show him some empathy!

Some related topics that we would discuss in upcoming posts:
1) On-Chip Variations and how they differ from PVT.
2) Temperature Inversion.
3) Factors affecting delays of standard cells.

Stay tuned for updates.


  1. thank you Mr.Naman Gupta U did a great job.....this lecture helped me a lot

  2. Thank you very much for explaining pvt so clearly, you mentioned that you will upload Temperature inversion. I am unable to find it. Can you send the link to that page.

    1. Thanks for pointing it out. I'll try and cover temperature inversion in a post very soon. Stay tuned for updates! :)

    2. For WORST COLD;BEST HOT PVT , those 2 corners are for TEMPERATURE INVERSION?
      Am I correct?

    3. Hi Ting Wang,

      Yes, you are right. Worst-Cold and Best-Hot emerged as signoff PVT corners for sub-65nm SoCs where temperature inversion was seen.


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  4. hanks for explanation in simple way but i have just one question i.e semiconductor has -ve temperature coefficient and hence resistance should decease and current should increase because of generation electron hole pairs.. is there is any relation which tells up to what temperature current will increase and after what it will decrease.. like "curie temperature" or something else

    1. Hi Sharma,
      The drain current is function of mobility and threshold voltage.
      Question: Why temperature inversion seeing in only lower technology (Ex 28nm and below).
      Answer: As we are going lower technology, scaling the channel length and power (VDD) is also, in the lower technology VTh will dominates on mobility so the effect will go reverse Since Vth is inversaly propartional to the (ID)Drain current. Please see below equation.
      Id = µ(T) * (Vdd – Vth(T))α

      Panchamukhi Ellur.

  5. Is it not wise to explain process wrt to SS, TT, and FF type of MOSFET ?

  6. hey you r a life saver bro...my lecturer made it so difficult...

  7. //Since electron movement is responsible for current flowing in the device, current would decrease with increase in temperature.//

    But in general, as electron movement is faster at higher temperature, current should be higher ??

    1. Electron mobility decreases because of the collisions and hence current decreases.

    2. I seen two statements made here

      1. Electron movement results in current
      2. Electron movement results in decrease of current due to collisions

      Am i missing any concept here ?

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  9. what you mean by 45 nm ?

  10. Hi Naman,
    Let's say in 28nm process. Channel length of Slow process differ process Fast Process ?

  11. Thank You Sir...,For your explanation about PVT cons in asic design