Clock Skew: Implication on Timing

Clock Skew is an important parameter that greatly influences the timing checks and you would often find the backend design engineers always keeping a close eye on the clock skew numbers. 

Clock Skew: The difference in arrival times of the clock signal at any two flops which are interacting with one another is referred to as clock skew. Having said that, please note that skew only makes sense for two flops which are interacting with one another, i.e. they make a launch-capture pair. 

If the clock at the capture flop takes more time to reach as compared to the clock at the launch flop, we refer to it as Positive Clock Skew. And when the clock at capture flop takes less time to reach the clock at the launch flop, we refer to it as Negative Clock Skew.

The figure below describes positive & negative clock skew. Assume the delays of clock tree buffers to be the same.

How does clock skew impact the timing checks, in particular, setup and hold? Consider the above example where FF1 is the launching flop and FF2 is the capturing flop. If the clock skew between FF1 and FF2 was zero, the setup and hold checks would be as follows:

• Positive Skew: Now imagine the case where clock skew is positive. Here, clock at FF2 takes more time to reach as compared to the time taken by the clock to reach the FF1. Recall that the setup check means that the data launched should reach the capture flop at most setup time before the next clock edge. As evident in the below the data launched from FF1 gets an extra time equal to the skew to reach FF2. Hence setup is relaxed! However, hold check means that data launched should reach the capture flop at least hold time after the clock edge. Hence, the hold is further made critical in case of positive skew. Read the definitions again and again till you grasp it!!

• Negative Skew: Here, clock at FF1 takes more time to reach as compared to the time taken by the clock to reach the FF2. As evident in the below the data launched from FF1 gets lesser time equal to the skew to reach FF2. Hence setup is more critical! However, hold is relaxed!
  
  Some Key Points to Note:
• Setup is the next cycle check, and positive skew relaxes the setup check and negative skew further tightens it.
• Hold is the same cycle check, and negative skew relaxes the hold check and positive skew further tightens it.
• Very rarely would one come across a path that is both setup as well as hold critical. Setup becomes critical when data path is huge or you have a large negative skew; and hold becomes critical when either data path is minimal or you have a large positive skew. Both these conditions are mutually exclusive and very rarely does they manifest themselves simultaneously. It is often a case when the uncommon clock path is significant. We shall discuss it in detail later.

Puzzle: Fixing Timing Violation

Timing Violation can manifest due to a plethora of reasons. And it is important for an STA Engineer to understand the violating path and model the constraints properly before providing them to the Synthesis/PnR tools for optimization. Unnecessary optimization should be avoided because:

• To save on the die area;
• To save on the leakage power;
• To prevent unnecessary congestion.

The figure below shows a scenario. Assume the clock period to be 8ns and the setup time of the capture flop (here, FF3) be 0ns and the clock-to-Q delay of the launch flops (here, FF1 & FF2) be 0ns. The violating path is shown in the figure. The negative slack is 1ns. 

How would you fix the above violation? Please note that there are many possible solutions; but one only solution adheres to the above discussed constraints of leakage power, area and congestion.

Puzzle: Identify the Issue with Circuit Topology

With the symbols having their usual meaning, identify the issue with this circuit topology.

[Hint]: Think from the timing perspective, and not the functional perspective.

You may answer the following:

• Issue with the topology.
• And in which kind of timing violation will the issue manifest itself while timing analysis.
• Possible modification(s) to solve the issue.

Sample Problem on Setup and Hold

In the post Timing: Basics, we discussed about the basics of setup and hold times. Why is it necessary to meet the setup and hold timing requirements. And how frequency affects setup but does not affect hold.

Let us understand the concept with an example:

I hope the above waveforms are self explanatory.
Setup Slack in the above case (as inferred from the waveforms as well) is:

Setup Slack = Tclk - T(clk-2-q) - Tdata - T(su,FF2)

If this setup slack is positive, we say that setup time constraint is met. Note that setup slack depends upon the clock period and hence in turn frequency at which your design is clocked.

Let us consider hold timing:

Hold Slack = Tdata + T(clk-2-q) - T(ho,FF2)

As evident from the above equation, hold slack is independent of the frequency of the design.

Note:

• Setup is the next cycle check, we would take the setup time T(su,FF2) of FF2 into account while finding setup slack at input pin of FF2.
• Hold time is the same cycle check, we would take the hold time T(ho,FF2) of FF2 into account while computing the hold slack at input pin of FF2.

Try and grasp this example. I shall introduce the concept of clock skew next.

Timing: Basics

In a few earlier posts, we have already mentioned timing. It's time to discuss it formally.

Timing is a constraint that must be met so that the design functions the way it was meant to.

• What will happen if the timing constraints are met?
  You can be pretty sure that the device will function correctly at the frequency that was intended.
• What will happen if the timing constraints are not met?
  Device will not function correctly at the intended frequency. And it might or might not function at a slower frequency.

Pretty confusing? Don't worry. Read on.

Consider the following digital circuit. Two rise-edge triggered flops a and b, fed by a clock signal CLK, talking to each other. Output of Flop a after being processed by combinatorial logic Comb is reaching the input of Flop b.

How does the above circuit work? Consider the two waveforms which are the clock signals at flop a and b respectively. Flop a samples the input data IN at rising clock edge 1a and this data is captured by Flop b at the clock edge 2b. Similarly, data sampled and launched by the flop a at clock edge 2a is captured by flop b at 3b. 

As long as this launching and capturing relationship is maintained correctly, our timing constraint is also met and device would function perfectly fine! But the question: What actually is this timing constraint?

The data launched at edge 1a has to do undergo the following delays before it reaches the input of flop b.

Clock to q delay of Flop a and delay of the combinatorial logic Comb. 

And it should reach the input of flop b a at least some time before the edge 2b reaches the clock pin of Flop b. This time is called Setup Time. 

Also, we have to make sure that the data launched by Flop a at clock edge 1a is not captured by Flop b at clock edge 1b (it needs to be captured at 2b). So, the data must reach the flop b at least some time after clock edge 1b reaches Flop b. This time is called Hold Time.

Read the above two lines again. 

Same would be the relationship for other edges. Setup checks: 2a-3b; 3a-4b. Hold checks: 2a-2b; 3a-3b and so on.

Setup and Hold are the bread and butter of every backend design engineer. But why should the data reach some time before or after some clock edge? Where do these times come from? What exactly is the origin of setup and hold times? I do not mean any disrespect, but the answer to this question can puzzle even an experienced design engineer and I assure you that we will take this up in detail very soon.

For now, convince yourself that:

• Setup is a next-cycle check while hold is the same cycle check.
• Setup is dependent on the period (and hence frequency) at which your flip-flops are clocked while hold checks are frequency independent.

A direct ramification of the above statement is that setup violations can be fixed by lowering the operating frequency of the design. But hold violations cannot be fixed that way! I shall explain the Origin of Setup and Hold times soon. Also, I would like to take up some examples that would corroborate the concepts that I explained in this post.

PVTs and How They Impact Timing

PVT is acronym for Process-Voltage-Temperature.

PVTs model variations in Process, Voltage and Temperature. There's other term OCV which refers to On-Chip Variation. PVTs model inter-chip variations while OCVs model intra-chip variations. 

We'll talk about OCVs in some other post.

Let's talk about PVTs in detail:

1) Process: You must have heard people talking in terms of process values like 90nm, 65nm, 45nm and other technology nodes. These values are characteristic of any technology and represents the length between the Source and Drain of a MOS transistor that you might have studied in your under-grad courses. While manufacturing any die, it has been seen that the dies that are present at the center are pretty accurate in their process values. But the ones lying on the periphery tend to deviate from this process value. The deviation is not big, but can have significant impact on timing.

Recall from your undergrad courses the following formula for current flowing in a MOS transistor:

                                             

L represents the process value. For same temperature and voltage values, current for 45nm process would be more than current for 65nm process.

More is the current, faster is the charging/discharging of capacitors. And this means, delays are less.

2) Voltage: The voltage that any semiconductor chip works upon is given from outside. Recall while working on breadboards in your labs, you used to connect a 5V supply to the Vcc pin of your IC. Modern chips work on very less voltage than that. Typically around 1V-1.2V.

This voltage must be the output of either a DC source or maybe the output of some voltage regulator. The output voltage of voltage regulator might not be a constant over a period of time. Let's say, you expected your voltage regulator to give 1.2V, but after 4 years, it's voltage dropped down to 1.08V or increased up to 1.32V. So, you gotta make sure your chip is working well between 1.08 and 1.32V!!

This is where the need to model Voltage variations come into picture.

From the same equation as above, it can be seen that more is the voltage, more is the current. And hence, delays are less.

3) Temperature: The ambient temperature also impacts the timing. Let's say you are working on a gadget in Siachen glacier where temperature can drop down to -40 degrees centigrade in winters and you expect your device to be working fine. Or maybe you are in Sahara desert, where ambient temperature is +50 degrees and your car engine temperature is +150 degrees and again you expect your chip to working fine. While designing, therefore, STA engineers need to make sure that their chip will function correctly in the temperatures between -40 to +150 degrees.

Higher is the temperature, more is the collision rate of electrons within the device. This increased collision rate forbids other electrons in the periphery to move. Since electron movement is responsible for current flowing in the device, current would decrease with increase in temperature. Therefore, delays are normally more at higher temperatures.

For technology nodes below 65nm, there's a phenomenon called TEMPERATURE INVERSION, where delays tend to increase with decreasing temperature. We shall talk about the same later. Don't get confused with it here.

WORST PVT: Process worst-Voltage min- Temperature-max

BEST PVT:  Process best-Voltage max- Temperature-min

WORST COLD PVT: Process worst-Voltage min-Temperature min

BEST HOT: Process best-Voltage max-Temperature max

STA engineers are responsible for closing the timing ( i.e. setup and hold ) at all these PVT corners.

So, next time you hear an STA engineer cribbing about his timing status across multiple PVTs, please show him some empathy!

Some related topics that we would discuss in upcoming posts:
1) On-Chip Variations and how they differ from PVT.
2) Temperature Inversion.
3) Factors affecting delays of standard cells.

Stay tuned for updates.