## July 07, 2012

### Timing: Basics

In a few earlier posts, we have already mentioned timing. It's time to discuss it formally.
Timing is a constraint that must be met so that the design functions the way it was meant to.

• What will happen if the timing constraints are met?
You can be pretty sure that the device will function correctly at the frequency that was intended.
• What will happen if the timing constraints are not met?
Device will not function correctly at the intended frequency. And it might or might not function at a slower frequency.
Pretty confusing? Don't worry. Read on.

Consider the following digital circuit. Two rise-edge triggered flops a and b, fed by a clock signal CLK, talking to each other. Output of Flop a after being processed by combinatorial logic Comb is reaching the input of Flop b.

How does the above circuit work? Consider the two waveforms which are the clock signals at flop a and b respectively. Flop a samples the input data IN at rising clock edge 1a and this data is captured by Flop b at the clock edge 2b. Similarly, data sampled and launched by the flop a at clock edge 2a is captured by flop b at 3b.

As long as this launching and capturing relationship is maintained correctly, our timing constraint is also met and device would function perfectly fine! But the question: What actually is this timing constraint?

The data launched at edge 1a has to do undergo the following delays before it reaches the input of flop b.
Clock to q delay of Flop a and delay of the combinatorial logic Comb.
And it should reach the input of flop b a at least some time before the edge 2b reaches the clock pin of Flop b. This time is called Setup Time.
Also, we have to make sure that the data launched by Flop a at clock edge 1a is not captured by Flop b at clock edge 1b (it needs to be captured at 2b). So, the data must reach the flop b at least some time after clock edge 1b reaches Flop b. This time is called Hold Time.

Read the above two lines again.
Same would be the relationship for other edges. Setup checks: 2a-3b; 3a-4b. Hold checks: 2a-2b; 3a-3b and so on.
Setup and Hold are the bread and butter of every backend design engineer. But why should the data reach some time before or after some clock edge? Where do these times come from? What exactly is the origin of setup and hold times? I do not mean any disrespect, but the answer to this question can puzzle even an experienced design engineer and I assure you that we will take this up in detail very soon.

For now, convince yourself that:
• Setup is a next-cycle check while hold is the same cycle check.
• Setup is dependent on the period (and hence frequency) at which your flip-flops are clocked while hold checks are frequency independent.
A direct ramification of the above statement is that setup violations can be fixed by lowering the operating frequency of the design. But hold violations cannot be fixed that way! I shall explain the Origin of Setup and Hold times soon. Also, I would like to take up some examples that would corroborate the concepts that I explained in this post.

1. sir when Flop a samples the input data IN at rising clock edge 1a and this data is captured by Flop b at the clock edge 2b. why not flop b capture data at 2a?

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2. Here a and b signifies the clocks of flop A and flop B. How can a flop capture its own data in next clock cycle?

2. why is hold timing checked at 1b and why not at 2b???

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4. Excellent description! Thank you :)

5. This is a good and simple article. It solved one of my query. Thanks.