In the post Factors Affecting Delays of Standard Cells, we talked about the clock transition and the way it impacts setup and hold times.
While building our clock tree we ensure that clock transition is as low as possible.
VLSI SoC Design: Concepts, Perspective & Implementation
The power would also get impacted as the transition degrades.
ReplyDeleteYes! That's correct, Shruti!
DeleteFor readers: Specifically, the short-circuit power component of the dynamic power would increase. Clock signal being the highest toggling frequency signal in the design which alone corresponds to >50% of the dynamic power, having a bad transition at clock tree cells would result in a terrible power-hungry design!!
There's one more reason: Noise.
Any degradation in the clock net transition would elongate the timing window, and hence the probability of clock nets acting as aggressor to surrounding victim data nets would increase. [You might see a massive jump in violations post-SI].
Hi Palindrome,
DeleteNice blog .
"While building our clock tree we ensure that clock transition is as low as possible." -- as low as possible is not the right statement , if the transition is very sharp (l10-50ps) , then the cell power increases. there is generally a point which will give u a minima for power at lower transitions (50-150ps) depending on your cell library .
Thanks, Anonymous. :)
DeleteAre you talking the addition of extra clock buffers needed to achieve this very sharp clock transition responsible for increase in power? If so, it should be independent of cell library/design technology node.
In this case, an individual clock buffer might contribute less, but overall impact (because of large number) would be detrimental. Please clarify.
What you're talking about is little different. I haven't seen it in the technology nodes that I have worked on. Would love to discuss more @ my.personal.log@gmail.com
I would like to add that the minima for transitions are selected also keeping in mind the Electromigration effects of a very sharp transition, apart from the extra power you may get by addition of the extra buffer cells.
ReplyDeleteThanks for pointing it out, Shruti. This point was lost in the hindsight of my memory.
DeleteThat indeed is the trade-off because of which one cannot have a very sharp clock transition. Many designers also tend shield the clock tree with power rails to mitigate the adverse effect of Electromigraton.
Not only electromigration, this will also increase the dynamic power as well, as minimum skew(of clock tree) with best slew is deadly combination for dynamic IR drop.
DeleteSo, there should be trade of between, min skew - min slew - dynamic IR drop, for optimum performance.
That summed up the entire chain of comments! Thanks!
Deletecan anyone of you suggest an article or book best explaining this concept of selecting transition or slew. and How does it affect the dynamic power.
DeleteThis was a very good discussion indeed
Thanks!
DeleteCould you please point out what you require more specifically? I don't think you'd be able to find any book with such a pointed discussion. I might be able to answer any specific queries or maybe refer to you some article.
Please help me to help you! :)
Hello everyone
DeleteI found this blog recently on internet.So maybe I am little late in putting my queries.But can anyone explain in how is transition time at the clk inv affecting EM & dynamic power consumption
appreciate your help!!!
thanks
Hi Saumitra,
DeleteFaster clock transition (numerically low value) means that the electric field experienced by the electrons while their transit along the wires is high. Alternatively, one can say that since the velocity with which the electrons are moving is high, their momentum (or perhaps energy) is high. These high-momentum electrons have the ability to displace the atoms of the device (when the device is operating over a long period of time). This displacement of atoms within the device might cause shorts at some places, and opens at other places. This is indeed the electromigration.
Now, let's link it with power. Since your signal is going high pretty fast, meaning in a small time, it means that the current drawn by the device is high. Power is simply VDD multiplied by the current drawn by VDD. It means, faster slew would mean higher dynamic power consumption.
-Naman
Thanks Naman for a very quick reply
DeleteBut, the reason that you gave applies equally for any cell not just clk cell.It is just that the clk cells have to change their state more frequently
-Saumitra
Yes, exactly! Clock is the signal which has the highest toggling frequency, and it does so throughout the lifetime of the chip. No wonder why clock nets are more susceptible to electromigration than any other nets.
DeleteMoreover, clock power constitutes close to 40% of the total dynamic power consumed in the entire SoC.
-Naman
just taking a hypothetical case here
DeleteThere is high frequency clock(f1) with lesser transition time(t1) &
there is comparatively slower clock(f2) with very high transition time(t2)
i.e ... f1>f2 & t1<t2
where do you think the chances of EM happening is more for a given period of operation
Well, that's hard for me to quantify and might be a topic for a case study. My bet would be that they both are gonna have equal impact on electromigration.
DeleteIn case you come across the answer, please enlighten me as well.
-Naman
If we assume that duty cycle of both the clocks are same, then the avg. current of slower clock(f2) is higher.
Deletei.e Avg ( I1 < I2)
that means for a given period of operation, the clock n/w with lower clock frequency is going to suffer EM
plz add your comments
thankyou
If the slew/transition's were really bad, it can severely impact the duty cycle and shorten the good pulse width. An FF can potentially fail to work if the min-pulse width requirement is not met. That's why you see min-pulse width violations in your all_violators reports in timing analysis tools (PT) etc. No setup or hold violation can catch this!
ReplyDelete-D
if the transition time is poor that mean the clock cell delay will degrade. Which means insertion delay will be high. Higher insertion delay means the path will be more susceptible to OCV thus creating more setup and hold violations. Closing timing will be a pain and one will have to use very strong cells to fix hold and setup. Thus increasing power.
ReplyDeleteWould short circuit power in the clk buffers tend to lower when the clk edges are bad , because output takes longer time to start falling and will fall slower too.
ReplyDeleteHi Niketh,
DeleteI'm not sure I understand your question.. But yes, if the transition time (slew) is bad (numerically higher), then the short circuit power dissipated in the clock tree buffers (or for that matter, any buffer) would be more.
Great enlightening discussion.
ReplyDeleteHello Naman,
ReplyDeleteBelow is my view with dynamic power dissipation increase/decrease wrt transition time.
Dynamic power have two component : Short circuit current (Isc) and current charging load (Icl)
Considering Load Cap is same Cl and same frequency of clock f.
Tr is transition.
Isc depends on PMOS and NMOS sizes/parameters and Vdd. So it’s constants.
Pdyn = Psc + Pcl = Isc.Vdd.Tr.f + Cl.Vdd^2.f
1. Transition time small : Psc will be less as transition time is less because short circuit current will draw for very small time. Pcl will be same as it has to charge same load cap.
2. Transition time large : Psc will be more as transition time is more because short circuit current will draw for very more time. Pcl will be same as it has to charge same load cap.
So, i think with transition time more dynamic power increase.
One reason in previous comment is to improve transition Ipeak will increase (agree) but still Pcl power will remain same as it has to charge same load cap Cl (over the clock period ).
Please let me know if any is not wrong with above.
Thanks
Manish
sorry.. correcting typo. Please let me know if anything is wrong with above.
DeleteManish,
DeleteShort circuit power also depends on output load. The larger the load, the smaller the Psc, with same input slew.
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ReplyDelete