July 28, 2012

Design for Testability: The Need for Modern VLSI Design

DFT is the acronym for Design for Testability. DFT is an important branch of VLSI design and in crude terms, it involves putting up a test structure on the chip itself to later assist while testing the device for various defects before shipping the part to the customer.

Have you ever wondered how the size of electronic devices is shrinking? Mobile phone used to be big and heavy with basic minimal features back in 90s. But nowadays, we have sleek phones, lighter in weight and with all sorts of features from camera, bluetooth, music player and not to forget with faster processors. All that's possible because of the scaling of technology nodes. Technology node refers to the channel length of the transistors which form the constituents of your device. Well, we are moving to reduced channel lengths. Some companies are working on technology nodes as small as 18nm. Smaller is the channel length, more difficult it is for the foundries to manufacture. And more are the chances of manufacturing faults.

Possible manufacturing faults are: Opens and shorts.
The figure shows two metal lines one of which got "open" while other got "shorted". As we are moving to lower technology nodes, not only the device size is shrinking but that also enables to pack more transistors on the same chip and hence density is increasing. And manufacturing faults have become therefore indispensable. DFT techniques enable us to test these (other kinds as well) faults.

Kinds of defects:
  • Opens and shorts, as mentioned above, can cause functional failures. A kind of open and shorts, where any node might get shorted to ground is referred to as stuck-at-0 (SA0) fault or in cases where the node might get shorted to the power supply is referred to as stuck-at-1 (SA1) fault.
  • Speed Defect: May arise due to coupling of a net with the adjacent net and hence affecting the signal transition on it.
  • Leakage Defect: Where a path might exist between the power supply and ground and this would cause excessive leakage power dissipation in the device.
In a nutshell, DFT techniques are important especially for sub-deep micron technology nodes (i.e. below 90nm). And it can prevent shipping any defective part to be customer, which instead would have caused revenue and goodwill loss for the semiconductor design companies.


  1. Can you please tell me what do you mean by "net" ?

    1. Net is nothing but a metal interconnect. Think of it as a metal wire that is used to join the output if one standard cell to the input of another standard cell. Obviously, the size of this wire would be in microns!!

  2. Please let know which fault models detect which defects and how are they mapped

  3. Please let know which fault models detect which defects and how are they mapped

  4. Can you tell me how coupling effect the signal transition