In this post, we would talk about the factors that affect the delays of standard cells. Before starting with the discussion, it would be prudent to discuss what is meant by Timing Arcs:
Timing Arcs: A timing arc represents the direction of the signal flow from usually an input to an output. They may be combinational or sequential. Combinational arcs represent the signal flow in combinatorial cells like AND, NAND, OR gates. Sequential arcs represents the signal flow in Flip Flops and they usually have a control signal like CLOCK associated with them. Third type that is closely related to sequential arcs are the setup and hold arcs. They represent the setup and hold requirements and in general, do not represent any signal flow.
The information about these timing arcs come from the timing library (.lib) files.
Let's turn our attention back to delays.
Consider an AND gate. As discussed above, A to Z is a combinational timing arc. The delay of this arc is picked up from the .lib. This .lib is then read by the timing tools in timing reports.
This delay depends on primarily 2 factors:
1. The input slew or the transition at A pin.
2. The output load or the capacitance at the Z pin.
Note that the output load is the sum total of the input capacitance of the cells connected to the node Z and also the net capacitance of all such nodes.
Output Load = Input Cap of all cells at the fan-out of Z + Total net capacitance of the nets connected to node Z.
Delay is directly proportional to the input transition and the output load.
1. More is the output cap, more time the cell would require to charge/discharge that capacitance. And hence, delays would be more.
2. More is the input transition, more time the cell would require to change the output after processing the input value.
1. More is the output cap, more time the cell would require to charge/discharge that capacitance. And hence, delays would be more.
2. More is the input transition, more time the cell would require to change the output after processing the input value.
You would note that explanation behind delays just boil down to charging/discharging of the capacitors!! Once you befriend them, you would be able to deduce half the concepts intuitively.
We are now set to discuss the delays of timing arcs of a flip-flop.
1. Clock-to-Q delay: As expected, it depends upon the clock transition and the load at the output Q. It may sound surprising, but clock-to-q delay does not depend upon the transition at the D input.
2. Setup and Hold time: Setup and Hold time depend upon the transition value at clock pin and transition value at D pin. It does not depend on the output load.
Some surprises might be yet to unfold. Read on.
1. Clock-to-q delay is directly proportional to the clock transition and the output cap at Q.
1. Clock-to-q delay is directly proportional to the clock transition and the output cap at Q.
2. Setup time is directly proportional to input transition at D and inversely proportional to the clock transition. Recall the definition of setup time. More is the clock transition time, more time you are allowing for the input at D to settle setup-time before the clock transition.
3. Hold time is inversely proportional to input transition at D and directly proportional to the clock transition. Again, recall the definition of hold time. More is the clock transition time, greater is the possibility that the D input might change in the hold window after clock transition.
I hope I was able to explain this stuff clearly. In case of any doubts, please feel free to post them here.
this is really wonderful ! Havent met someone these days who had so much clear idea on these things. Awesome ! great job and thanks for sharing it
ReplyDeleteHello Vivek. Thanks a lot!! :)
DeleteI started writing all this stuff because I made a promise to myself long time back. And now, it pushes me to read new papers and related stuff.
By the way, I sneaked into your profile. Apologies for that! Loved your blog as well. There seems to be a lot of buzz around FinFets these days! Your post on the same helped me get started!
Thanks!! :)
Thanks Naman
Deleteyour comment means a lot to me. I just wish to make everything simple and uncomplicate things.
in this post i learn so many thing... really superb..
Deletethanks to Naman
"there are a few scenarios
ReplyDeletewhere the input threshold (used for measuring delay) is significantly different
from the internal switching point of the cell. In such cases, the delay
through the cell may show non-monotonic behavior with respect to the input
transition time - a larger input transition time may produce a smaller
delay especially if the output is lightly loaded."
is this true? if true can any one explain how ..pls..
hi naman,
ReplyDeletei am a bit confused regarding your explanation on the hold time.because hold time doesn't depend on clock,so how come it depends on clock tran.please correct me if i am wrong and please clarify my doubt?
thanks®ards,
mk
Intention of saying is Clock Skew plays a significant role.
DeleteHold timing check usually won't depend on the clock period. But the hold time of a sequential cell, do depend on the clock transition time. After all, the value at D pin moves to Q pin, during a clock edge!
DeleteHi all,
ReplyDeleteCan anyone explain me how IR drop affects the clock path and data path?
My answer is due to decrease in voltage clock transition time increases and setup time of the flop increases and this becomes critical for setup slack. And in data path decrease in V increases cell delay and again it's critical for setup slack.
Is my analysis right?
M not able to conclude on hold time of the flop.
During clock tree synthesis, the buffers and inverters are added along the clock path to balance the skew. IR drop on buffers and inverters of clock path will cause delay in arrival of clock signal, causing hold violation.
Deletefor hold timing as the volatge nedded for standard cell drops from a original value as ir drop is there in power rails so the actual voltage needed for std cell decreases so current drawn to charge cap decreses so cell delay increases so hold will meet in that path where it is critical but due to ir drop setup genrally affects but not hold !!.Due to ir drop we maily encounter problem with noise margins as noise margin decreases as the voltage decreases so main effect is noise margin !!
ReplyDeleteClock-to-Q delay: As expected, it depends upon the clock transition and the load at the output Q. It may sound surprising, but clock-to-q delay does not depend upon the transition at the D input.
ReplyDeleteIf i'm not wrong this statement is subject to the following conditions:
1. The flop is typical transmission gate based flip flop. A NAnD/nor master slave may have D pin transition impacting the slew propagation through the output pin.
2. D pin is not getting used to gate the clock or output logic.
Excellent explanation
ReplyDeletehow slow clock tran will increase penalty on hold timing as it will increase launch clock path delay also. so why we are looking at only capture flop clock path?
ReplyDelete56
ReplyDelete