tag:blogger.com,1999:blog-2547531593106636954.post382415364043129741..comments2024-03-27T00:15:35.843-07:00Comments on VLSI SoC Design: Factors Affecting Delays of Standard CellsNamanhttp://www.blogger.com/profile/07902192684048580280noreply@blogger.comBlogger14125tag:blogger.com,1999:blog-2547531593106636954.post-74943097257606070262022-03-13T22:26:34.645-07:002022-03-13T22:26:34.645-07:00how slow clock tran will increase penalty on hold ...how slow clock tran will increase penalty on hold timing as it will increase launch clock path delay also. so why we are looking at only capture flop clock path?Neha Tiwarihttps://www.blogger.com/profile/04819104054295105722noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-5955669404623002962019-08-26T15:27:41.455-07:002019-08-26T15:27:41.455-07:00During clock tree synthesis, the buffers and inver...During clock tree synthesis, the buffers and inverters are added along the clock path to balance the skew. IR drop on buffers and inverters of clock path will cause delay in arrival of clock signal, causing hold violation.vinayhttps://www.blogger.com/profile/16862422865574454151noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-58772608410595894462018-08-29T12:14:57.488-07:002018-08-29T12:14:57.488-07:00Excellent explanation
Excellent explanation<br />Anonymoushttps://www.blogger.com/profile/09407699488918548107noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-582660697701708822017-01-29T02:01:31.919-08:002017-01-29T02:01:31.919-08:00Hold timing check usually won't depend on the ...Hold timing check usually won't depend on the clock period. But the hold time of a sequential cell, do depend on the clock transition time. After all, the value at D pin moves to Q pin, during a clock edge!Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-66059001040826347112016-06-15T12:43:38.893-07:002016-06-15T12:43:38.893-07:00Clock-to-Q delay: As expected, it depends upon the...Clock-to-Q delay: As expected, it depends upon the clock transition and the load at the output Q. It may sound surprising, but clock-to-q delay does not depend upon the transition at the D input.<br /><br />If i'm not wrong this statement is subject to the following conditions:<br /> 1. The flop is typical transmission gate based flip flop. A NAnD/nor master slave may have D pin transition impacting the slew propagation through the output pin.<br /> 2. D pin is not getting used to gate the clock or output logic.Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-59308756750652540812016-05-19T11:00:44.847-07:002016-05-19T11:00:44.847-07:00for hold timing as the volatge nedded for standard...for hold timing as the volatge nedded for standard cell drops from a original value as ir drop is there in power rails so the actual voltage needed for std cell decreases so current drawn to charge cap decreses so cell delay increases so hold will meet in that path where it is critical but due to ir drop setup genrally affects but not hold !!.Due to ir drop we maily encounter problem with noise margins as noise margin decreases as the voltage decreases so main effect is noise margin !!sumanthhttps://www.blogger.com/profile/08718361613246290823noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-45857373872293355152016-02-29T18:05:20.943-08:002016-02-29T18:05:20.943-08:00Hi all,
Can anyone explain me how IR drop affects ...Hi all,<br />Can anyone explain me how IR drop affects the clock path and data path?<br />My answer is due to decrease in voltage clock transition time increases and setup time of the flop increases and this becomes critical for setup slack. And in data path decrease in V increases cell delay and again it's critical for setup slack. <br />Is my analysis right?<br />M not able to conclude on hold time of the flop. Anonymoushttps://www.blogger.com/profile/06799230434784799314noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-59823015278782073602015-09-01T06:13:32.111-07:002015-09-01T06:13:32.111-07:00Intention of saying is Clock Skew plays a signific...Intention of saying is Clock Skew plays a significant role. <br />krishnahttps://www.blogger.com/profile/04341198889321733154noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-1358864249654958232015-06-17T15:15:31.189-07:002015-06-17T15:15:31.189-07:00hi naman,
i am a bit confused rega...hi naman,<br /> i am a bit confused regarding your explanation on the hold time.because hold time doesn't depend on clock,so how come it depends on clock tran.please correct me if i am wrong and please clarify my doubt?<br /><br /> thanks&regards,<br /> mkAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-15433729288080255082015-05-13T05:05:14.814-07:002015-05-13T05:05:14.814-07:00"there are a few scenarios
where the input th..."there are a few scenarios<br />where the input threshold (used for measuring delay) is significantly different<br />from the internal switching point of the cell. In such cases, the delay<br />through the cell may show non-monotonic behavior with respect to the input<br />transition time - a larger input transition time may produce a smaller<br />delay especially if the output is lightly loaded."<br />is this true? if true can any one explain how ..pls..Anonymoushttps://www.blogger.com/profile/17525743011036480497noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-17961115692971573342014-05-22T01:08:32.652-07:002014-05-22T01:08:32.652-07:00in this post i learn so many thing... really super...in this post i learn so many thing... really superb..<br />thanks to Naman pradeep manthenahttps://www.blogger.com/profile/16938067196683322819noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-66418444106351512272013-06-24T22:22:25.965-07:002013-06-24T22:22:25.965-07:00Thanks Naman
your comment means a l...Thanks Naman <br /> your comment means a lot to me. I just wish to make everything simple and uncomplicate things. vivekhttps://www.blogger.com/profile/01788403862390629929noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-15928272821637536302013-06-24T07:46:43.233-07:002013-06-24T07:46:43.233-07:00Hello Vivek. Thanks a lot!! :)
I started writing a...Hello Vivek. Thanks a lot!! :)<br />I started writing all this stuff because I made a promise to myself long time back. And now, it pushes me to read new papers and related stuff.<br /><br />By the way, I sneaked into your profile. Apologies for that! Loved your blog as well. There seems to be a lot of buzz around FinFets these days! Your post on the same helped me get started!<br /><br />Thanks!! :)<br />Anonymoushttps://www.blogger.com/profile/05066949277808318582noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-6941488504707835852013-06-24T04:43:33.068-07:002013-06-24T04:43:33.068-07:00this is really wonderful ! Havent met someone thes...this is really wonderful ! Havent met someone these days who had so much clear idea on these things. Awesome ! great job and thanks for sharing it vivekhttps://www.blogger.com/profile/01788403862390629929noreply@blogger.com