August 17, 2012

Puzzle: Identify the Issue with Circuit Topology

With the symbols having their usual meaning, identify the issue with this circuit topology.

[Hint]: Think from the timing perspective, and not the functional perspective.

You may answer the following:
  • Issue with the topology.
  • And in which kind of timing violation will the issue manifest itself while timing analysis.
  • Possible modification(s) to solve the issue.


  1. In order to avoid glitches @ the output of AND gate, the clock tree buffers delay should be always greater than the (CLK To Q delay of flop + comb delay ), other wise clock gating setup violation might manifest.

    1. Hello! Yes, that is right. But what about the clock gating hold? Won't it be an issue here?

      Thanks for your comment!

    2. You are asking about hold violation at register set?


    3. No! Here, I meant to highlight the hold violation at the input of the AND gate, where clock is being gated, and hence, more appropriately put, it is a clock gating hold violation.

  2. Hi palindrome! Can you please explain the problem in the above ckt more clearly. Thanks in advance :)

    1. Hello!

      There is a timing violation in the above circuit. As I mentioned in the above comment, it is a clock-gating hold violation at one input of the AND gate with respect to the clock at other input of the AND gate. In order to take care of the above mentioned violation, the designer must ensure that the enable is launched from the negative edge triggered flip-flop. You might want to review the post titled "Clock Gating Checks" to get a further insight into the problem.


  3. simulation tool will use a wrong point for hold check, so we need to explicitly mention
    set_clock_gating_path -hold 5 \
    -from [FF1] \
    -to [FF2]