tag:blogger.com,1999:blog-2547531593106636954.post3339748971293383899..comments2024-03-27T00:15:35.843-07:00Comments on VLSI SoC Design: Puzzle: Identify the Issue with Circuit TopologyNamanhttp://www.blogger.com/profile/07902192684048580280noreply@blogger.comBlogger8125tag:blogger.com,1999:blog-2547531593106636954.post-84789614882917130302021-08-08T11:06:09.367-07:002021-08-08T11:06:09.367-07:00HI, I am confused why setup and hold coming up if ...HI, I am confused why setup and hold coming up if its a normal and gate. <br />Is it an ICG instead of a simple AND gate?Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-72884857972738931482015-01-15T03:34:51.454-08:002015-01-15T03:34:51.454-08:00simulation tool will use a wrong point for hold ch...simulation tool will use a wrong point for hold check, so we need to explicitly mention<br />set_clock_gating_path -hold 5 \<br />-from [FF1] \<br />-to [FF2]Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-10176946404662051462013-08-25T03:08:03.664-07:002013-08-25T03:08:03.664-07:00Hello!
There is a timing violation in the above c...Hello!<br /><br />There is a timing violation in the above circuit. As I mentioned in the above comment, it is a clock-gating hold violation at one input of the AND gate with respect to the clock at other input of the AND gate. In order to take care of the above mentioned violation, the designer must ensure that the enable is launched from the negative edge triggered flip-flop. You might want to review the post titled "Clock Gating Checks" to get a further insight into the problem.<br /><br />Thanks!Anonymoushttps://www.blogger.com/profile/05066949277808318582noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-91694222042695437262013-08-24T04:51:54.222-07:002013-08-24T04:51:54.222-07:00Hi palindrome! Can you please explain the problem ...Hi palindrome! Can you please explain the problem in the above ckt more clearly. Thanks in advance :)Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-91171259961145351912013-03-09T01:28:06.275-08:002013-03-09T01:28:06.275-08:00No! Here, I meant to highlight the hold violation ...No! Here, I meant to highlight the hold violation at the input of the AND gate, where clock is being gated, and hence, more appropriately put, it is a clock gating hold violation.Anonymoushttps://www.blogger.com/profile/05066949277808318582noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-13805588035838108142013-03-07T23:08:39.755-08:002013-03-07T23:08:39.755-08:00You are asking about hold violation at register se...You are asking about hold violation at register set?<br /><br />=Bond007Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-19012844061972480342013-02-02T22:28:20.105-08:002013-02-02T22:28:20.105-08:00Hello! Yes, that is right. But what about the cloc...Hello! Yes, that is right. But what about the clock gating hold? Won't it be an issue here? <br /><br />Thanks for your comment!Anonymoushttps://www.blogger.com/profile/05066949277808318582noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-847492758414289732013-02-02T20:42:42.230-08:002013-02-02T20:42:42.230-08:00In order to avoid glitches @ the output of AND gat...In order to avoid glitches @ the output of AND gate, the clock tree buffers delay should be always greater than the (CLK To Q delay of flop + comb delay ), other wise clock gating setup violation might manifest.Anonymousnoreply@blogger.com