March 09, 2013

OCV vs PVT

In the post PVTs and How They Impact Timing, we talked about the confluence of the Process-Voltage and Temperature factors and their impact on timing. I would urge the readers to go through the post in order to grasp the difference between two key terminologies used in the VLSI industry- 

  • OCV: On Chip Variation;
  • PVT: Process, Voltage and Temperature
While PVTs are inter-chip variation which depend largely on external factors like: the ambient temperature; the supply voltage and the process of that particular chip at the time of manufacturing. Like PVTs, OCVs are also variations in process, voltage and temperature. But, hey, where's the difference? OCVs are intra-chip variations! To elucidate more about the OCVs, let's talk in terms of chips!

  • Variation in Process: There are millions of devices (standard cells); and probably billions of transistors packed on the same chip. You can expect every single transistor to have the same process or the channel length! If we say that the chip manufactured exhibits, let's say, worst process, it means that the  channel length tends to deviate towards the higher side. This variation may be more for some transistors and less for some. It can be a ponderous task to quantify this variation between the transistors of the device, and is often modeled as a percentage deviation from the normal.
  • Variation in Voltage: All the standard cells need voltage supply for their operation. And voltage is usually 'tapped' from the voltage rail via interconnects which have a finite resistance. 


In two parts of the chip, it is fairly probable for the interconnect length to be different, resulting in a finite difference in the resistance values and hence the voltage that the standard cells actually receive. As evident above, the voltage received by the standard cells on the right would be less as compared to those on the left.

This variation would be less, probably of the order of a few mili-volts, but is can be significant, is again modeled as OCV.
  • Variation in Temperature: Some parts of the chip can be more densely packed or might exhibit more active switching ss compared to the other parts. In these regions, there is a high probability of the formation of localized 'HOT SPOTS' which would result in increased temperature in some localized areas of the chip. Again, this difference might be order of a few degree centigrade, but can be significant.
All the above mentioned variations are examples of On-Chip-Variations. And usually, these variations are modeled as a fixed percentage of delays. For examples, a 4% OCV derate would mean, that the delays of cells in the data path are inflated by 4% while doing setup analysis and decreased by 4% while doing hold analysis. Same methodology is applied for the clock paths. However, it would be different for launching and capture clock paths. That also gives rise to an interesting topic of Common Path Pessimism Removal which we shall take up shortly. 

9 comments:

  1. 4% derate is handled in timing constraints or in cell delays?

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  2. 4% derate is handled in timing constraints. And this constraint would increase/decrease the cell delays by 4%, as the case may be, to model the additional pessimism required to incorporate the effect of OCV.

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  3. Can someone tell how all these factors affect propagation delay and hence the duty cycle of pulse

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    1. Hello.

      The duty cycle (of let's say clock) would depend on the rise and fall times of the clock signal. These transition times (also called slews) would depend on PVTs. You might like to review the post: Factors Affecting Delays of Standard Cells.

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  4. Hi . Can you please correct me if i am wrong.
    Can we say PVT differences within a chip is called OCV ?

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  5. OCV itself is a PVT variation. PVT term is used to distinguish with different simulation/analysis conditions/corners viz device being slow/fast (n/p), temperature and voltage fluctuation. With technology shrinking and designs getting bigger and bigger, every single kind of variation/deviation possibility now can be witnessed in a single die/chip, which earlier was found in different chips, chips from different wafers etc. Now a reasonably large chip can have devices within it at two different locations operating with different PVT (FF, SF, FS, SS, TT) etc.

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    1. Read "simulation/analysis" as "operating" conditions.

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  6. how we decide number of corners?
    how many corners are present in any sta sign off?

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