March 17, 2013

Low Power FSMs

Low Power design is the need of the hour! The post: Need for Low-Power Design Methodology gives an insight into the intent and need for the modern design to be power aware. The subsequent posts on Clock Gating and Power Gating under the tab Low Power Methodology discuss some ways in which the the SoC can be designed for low power. In this post, we will consider one such low power design of an FSM which can be generalized to design any low power sequential circuit.

Consider the following generalized design of a traditional and a low power FSM:

Let's talk about the basic building block that we have used here. The OR gate acts as an clock gate to the flop. The flop that we have used is a toggle flop. When enable = 0, the flop receives the clock, and the flop toggles its state. So, whenever we need to change the state of the flop, we can give a clock pulse.

Enough said! Let's now talk about a real example of a basic synchronous counter. And how we can design a low power synchronous counter using the above method.

In any binary counter:

• The lowest order bit toggles after every clock cycle.
• Any higher order bit toggles only when all the lower order bits are at logic 1.
Keeping this in mind, we can now build the low power counter!!

1. I believe the FF shown in the diagram should be -ve edge triggered FF as the clock gating shown is OR gate based.

1. Hi Vasanth,

Since it's an OR gate based clock gating, the FF should only be a +ve edge triggered flop. Else the output would be glitchy.

You might want to review the post: http://vlsi-soc.blogspot.in/2013/02/clock-gating-check.html

Please let me know in case I didn't understand your query well.

Thanks!

2. How STA is taking care in this case? All flops are having different clocks, how to constrain these clocks?
Also how to take care of DFT? I see, you are using the same signal as clock as well as data.