Till a few months back, I assumed that channel length and gate length were same terms used interchangeably. However, one of the classes that I took at USC cleared this doubt and I'm very thankful to my professor for explaining the subtle difference between the two.

The figure above shows the cross-section of an NMOS with it's source, drain, gate. Let's talk about the difference between gate length, channel length and the diffusion length.

While fabricating a MOS device, typically the poly gate is grown first using the minimum feature size mask which is characteristic of a particular technology node. After this, the source and drain are formed by ion-implantation of Phosphorus (n+). This is referred to as self-aligned process. After ion-implantation, there is some side diffusion of the implanted ions because of which, the n+ region extends up to a small width below the gate. This is referred to as the diffusion length or the diffusion width. The effective distance between the drain and the source where the channel would eventually be formed and the actual length an electron would travel from source to drain is called the Effective Channel Length! I encourage you to read up more about the steps in CMOS Fabrication for better understanding.

As evident from the above figure:

**Channel Length = Gate Length - 2 x (Diffusion Length)**
Well, that was theory! Now some practical discussion. :)

When we say that we have let's say a 28 nm technology node. Which of the above would be 28 nm? Well, it would be the GATE LENGTH! As pointed above, gate corresponds to the minimum feature size mask which is characteristic of a particular technology node!

When we say that we have let's say a 28 nm technology node. Which of the above would be 28 nm? Well, it would be the GATE LENGTH! As pointed above, gate corresponds to the minimum feature size mask which is characteristic of a particular technology node!

Now, let's say, this NMOS is operating in the saturation regime, and there's no pinch off yet. If you wish to find the saturation current flowing through the device, you'll have to use the channel length in the formula for the drain current which is a quadratic function of the gate-to-source voltage.

How do we find this channel length? For older technology nodes (like 250 nm), this diffusion used to be negligible as compared to the gate length. However, for advanced sub-micron technology nodes, the side diffusion length is typically 10% of the gate length. (Actual numbers may vary from one manufacturer to another). So, for 28 nm technology node, you might expect the actual channel length to be in the order of 20-22 nm.

clear clarification,Thanks.

ReplyDeleteYou're welcome, Nitesh.

DeleteThis is amazing and very different from the prejudiced belif. Thank you.

ReplyDeleteYeah, took me more than 4 years to realize this! :P

DeleteYou're welcome!

-Naman

Very well explained. I just came across your blog and started reading posts one by one. Thanks to you Naman. Kudos to your efforts for all these posts.

ReplyDeleteThanks, Karthik! :)

DeletePlease spread the word! :)

-Naman

At 28nm, channel lengths of std-cells typically available are 30,35,40 (all > 28nm) and not < 28nm. But you mentioned here channel length at 28nm is of the order 20-22nm. Is there any difference in the interpretation here of channel lengths?

ReplyDeleteHow 28nm be GATE LENGTH in this interpretation? If it is technology node, it has to be CHANNEL LENGTH!

ReplyDeletecorrect me if Iam wrong.

How to calculate the width of the transistor for 28nm technology

ReplyDelete