September 16, 2015

Puzzle: Vt Flavors of Standard Cells

Let's say you have the following flavors of standard cells (say NAND):

  • NAND2_HVT_X2 (A two-input NAND gate, of High-Vt and drive strength 2).
  • NAND2_HVT_X4
  • NAND2_HVT_X8
  • NAND2_LVT_X2
  • NAND2_LVT_X4
  • NAND2_LVT_X8
Can you help me arrange these cells in the decreasing order of their:
  • Area
  • Delay
  • Leakage Power
Also please answer the following:
  • Which cell(s) are you more likely to use on a setup-critical path?
  • Which cell(s) are you more likely to use on a hold-critical path?
  • Which cell(s) are you more likely to use in a chip with stringent low standby power specifications?
And the last question: which among the following do you think is responsible for different threshold voltage (Vt) characteristics of HVT and LVT cells:
  1. Different doping profiles of HVT and LVT cells.
  2. Different gate lengths of HVT and LVT cells. (Also called Gate Length Biasing).
  3. Both of the above.
  4. None of the above.
Hint: At some places, few quantities might be equal, so make sure you use equality instead of greater than.

Please post your answers in the comments below.


  1. Hi Naman..

    For the first question, in decreasing order:
    Area: H_X8=L_X8 > H_X4=L_X4 > H_X2>L_X2
    Delay : HX2> HX4> HX8> LX2> LX4> LX8
    Leakage Power: Just the opposite of above

    For setup critical path : LVT cells would be desirable ( to decrease the delay of data path).
    For hold critical path : HVT cells would be desirable (to increase the delay of data path).
    For low standby power specs : HVT cells would save on the leakage current and thereby static power.

    For the last question, both doping and gate lengths would be responsible for different Vt.


    1. Correction
      For the first question, in decreasing order:
      Area: H_X8=L_X8 > H_X4=L_X4 > H_X2=L_X2

    2. Dear Yankee,

      Your answer is absolutely correct, except for the last question. It's only the doping which is responsible for different Vt.

      Thanks for posting the answer. May you LLP. :)

    3. Gotcha! Thanks Naman.. for your prompt reply.
      I am a regular reader of your blog. Good work, man!

    4. For Hold
      HVT > SVT > LVT (single corner/not setup critical Low drive strength first )
      LVT > VT > HVT (x-corner/setup critical low drive strength later)

      For setup LVT > SVT > HVT (low drive strength later)
      For Power stringent
      (Design dependent)
      Usage of LVT cells may reduce total High VT area + dynamic power due to usage of smaller but faster cells in performance driven designs like core/gpu plus with the added benefit of lower cross-corner variation so lesser hold buffers.
      So LVT usage may rather reduce power.
      But if your design is not performance driven then HVT/SVT will help.

    5. Actually for qn 2:
      Delay :
      size n VT depends on the tech n libs:
      Delay :eg : HX2> LX2> HX4> LX4> HX8> LX8

      and for leakage power als applies the same phenomena.

    6. Hi
      I have a doubt... How can you be sure that Delay : HX4>LX2... In this case, the lower threshold voltage definitely helps the LVt but since the drive strength is higher for HVt, it might actually produce a greater current. If u say LX2<HX2 that's absolutely correct but saying LX2<HX4 is not absolute but rather relative.

  2. Super Like! A post explaining foundry nomenclature (like TSMC) of different cells would be even more helpful!

    1. Hi Bhog,

      Thank you so much! :)

      The nomenclature of standard cells is different for different foundries like TSMC, Global foundries. And even for the same foundry, it's different for two different technology nodes. I believe the nomenclature is not fixed.

      To give an overview, we might have just HVT, LVT cells for 90nm. But we typically have HVT, LVT, ULVT cells for 14nm and below. Nomenclature could be like AND2, or AN2. NAND2, ND2 and so on.. It is not at all consistent. Moreover, we might have a certain category of cells unheard of in the previous design technologies like the state retention flops, power gates, isolation cells etc!