Let's say you have the following flavors of standard cells (say NAND):
- NAND2_HVT_X2 (A two-input NAND gate, of High-Vt and drive strength 2).
Can you help me arrange these cells in the decreasing order of their:
- Leakage Power
Also please answer the following:
- Which cell(s) are you more likely to use on a setup-critical path?
- Which cell(s) are you more likely to use on a hold-critical path?
- Which cell(s) are you more likely to use in a chip with stringent low standby power specifications?
And the last question: which among the following do you think is responsible for different threshold voltage (Vt) characteristics of HVT and LVT cells:
- Different doping profiles of HVT and LVT cells.
- Different gate lengths of HVT and LVT cells. (Also called Gate Length Biasing).
- Both of the above.
- None of the above.
Hint: At some places, few quantities might be equal, so make sure you use equality instead of greater than.
Please post your answers in the comments below.