September 04, 2015

IDDQ Testing

IDDQ is the IEEE symbol for Direct Drain Quiescent Current and IDDQ Testing measures this current to discriminate between a good and a defective chip. But how could current be used to detect a fault? Read on!

IDDQ testing is gaining popularity among DFX (DFT, DFV, DFM etc condensed into DFX) engineers because it's cost effective and can detect faults which might be left undetected by traditional DFT techniques like the scan testing (stuck-at fault testing), atspeed testing (transition fault testing) or delay testing. IDDQ testing helps ascertain an extra degree of confidence that the manufactured chip is defect free and hence the defect level (the number of defective chips per million manufactured chips shipped to the customer) is low.

Principle: IDDQ testing is based on the principle that complimentary CMOS does not draw any current from the power supply when it's inputs are static (i.e. not switching). In reality, however, there exists a small leakage current which typically is orders of magnitude smaller than the switching current. By this definition, all CMOS circuits are 100% IDDQ testable. 

Faults detected by IDDQ tests:
  • Bridging Faults: Shorts between two nodes causing a voltage contention because they are being driven by two conflicting voltages. Sometimes also referred to as stuck-on faults.
  • Punch-through: Short between Drain and the source.
  • Resistive Shorts
  • Line and Gate Break Faults
  • Source or Drain Break Faults
  • Even some Delay Faults
  • Latch-Up
  • Stuck-open Faults,

Examples:

  • Bridging Fault: If there exists a short (which could perhaps be because of some extra metal caused by process variations) between two wires which are driving opposite logic values, the voltage at the node might be at any intermediate level between VDD and 0. In the worst case it could be stuck at VDD/2, causing metastability at the flip-flop and hence a functional failure. If the two inverters in the circuit below are driven to opposite values, there's a current flow from the power supply of one inverter to the ground of another which would be typically in the range of tens of micro-amps (as opposed to nano-amps leakage current). This anomaly can be detected by IDDQ testing.


  • Line Break Fault: If the input to any gate is broken (possibly because of mask misalignment), the input becomes floating. This floating input might attain any value which in the worst case might result in conduction through both NMOS and PMOS transistors, thereby resulting in a large current flow through the device.



The principle behind stuck-on faults, gate, drain and source break fault is fundamentally similar to the line break fault. 

Gate, drain and source break faults manifest inside the standard cells where there exists an open at either one or more of the transistor terminals, again causing a floating node and hence an unknown voltage value resulting in high current!

Refer to the post on Latch-Up to understand how does Latch-Up result in a high-current flow through the CMOS device. This high current flowing through the device can be propagated to the power rail and detected using IDDQ test vectors.

Caveat of IDDQ Testing: 
  • There might exist a few corner cases where a good circuit might be identified as a faulty by IDDQ testing. Such cases can be reverse-engineered to ascertain to be false, however, it might take a lot of effort and debug-time. Discussing such cases is beyond the scope of this blog post.
  • As mentioned earlier, IDDQ testing can be used for CMOS circuits. Dynamic Logic has been gaining a lot of attention in the recent years in high-speed applications. Dynamic Logic circuits cannot be tested using IDDQ testing because it exhibits precharge property where the output capacitance is charged every time in the precharge phase irrespective of the value at inputs (even if they are static!)


Comparison with other testing methodologies:
  • While other testing methodologies like scan and atspeed rely on detecting the voltage level at the node in question which is being tested for a desired fault, IDDQ testing senses current levels. 
  • Traditional testing methodologies rely on the two pillars of DFT namely: controlability and observability as the sensitized fault (controlability) needs to be propagated to the output (observability), in order to detect a fault. In IDDQ testing, all faults are propagated to the power supply which is much easier to do so. Hence, typically, only 2-3 test vectors are sufficient to achieve a 50% fault coverage for IDDQ testing.
  • Scan and atspeed testing require ATE (Automatic Test Equipment) to apply test patterns and receive the output of the DUT (Device Under Test). IDDQ tests require an off-chip current monitoring device, in addition to the ATE.
References: 
  • IDDQ Made Easy. CMOS IDDQ Test Methodology by Bob Duell, Systems Science Inc.
  • IDDQ Testing Outline. Lecture Slides by Dr. Wenben Jone, University of Cincinnati.

2 comments:

  1. Nicely collated!
    Can you also share some insight into ISSQ mode of testing (Built-in Current Sensors testing) and it's possible demerits?

    ReplyDelete
  2. QUANTUM BINARY SIGNALS

    Get professional trading signals sent to your cell phone every day.

    Follow our trades NOW and profit up to 270% per day.

    ReplyDelete