I've got this question multiple times- How do we fix timing violations on paths that have at least one node which is both setup critical and hold critical simultaneously. To answer that question, one must realize that (generally speaking) for the same PVT and same RC corner, there cannot be paths where all nodes are simultaneously setup and hold critical.
Let's take an example:
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| Test Case |
Now, if we buffer at node C, path from B to C which was already setup critical will start violating.
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| Buffering at C |
If we buffer at Node A, the path from A to D which was already setup critical would start violating.
What shall we do here now? Any suggestions? Thoughts? I'd like to hear from you and I'll post the right answer (at least one of the right answers soon!). Just like always, looking forward to engage in the comments section below.
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ReplyDeleteCould you change the Vt class of the cells. Make cell after node C (OR gate) a HVT and cell after node D (AND/NAND) a HVT ?
ReplyDeleteIf I change any cell to HVT, the paths will start violating because A to D; B to C; and B to D are already setup critical.
DeleteBut you said that for same PVT and same RC corner there won't be paths that are simultaneously setup and hold critical. So if in one corner if hold is critical you could change the cell to HVT as it wouldn't be setup critical in that corner.
DeleteI said there'll be no paths where "all nodes" are simultaneously setup and hold critical.
DeleteBut there can be one node which is simultaneously setup and hold critical for a particular RC and PVT corner.
None! Assume no external factors are affecting this path. :)
ReplyDeletecreate one more AND gate and feed same inputs "A&B", now we decoupled setup and hold from A&B. try to fix setup and hold arcs separately.
ReplyDeleteSorry now i am posting in detail,
DeleteCreate one more AND gate in parallel and feed same input A&B.
from first and gate output, take c branch.
from second gate output, take D branch.
now fix hold between A and C without affecting setup critical A to D Arc.
I hope in this way it will work but we have to take penalty on area by making one more AND gate on silicon.
That is indeed the right answer, and yes it will certainly incur some area penalty, but hopefully, such cases won't come too often too many! :)
DeleteThanks for posting the answer!
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DeleteWhat difference does adding buffer at source and adding buffer at sink make?
ReplyDeleteHi Naman,
ReplyDeleteI have a question. If there is long net between source and sink. If I am trying to decrease the delay should I add a buffer near to the source or near to a sink? How can a buffer reduce the delay?
Thanks
You are breaking the net to reduce the delay it means delay is coming due to high load on driver. So you can put the buffer near to sink.
DeleteNOTE: You have to figure out the appropriate location so that the buffer can drive the downstream load.
I hope it helps!
very good blog
ReplyDelete