Routing: Basics

Routing process determines the precise paths for nets on the chip layout to interconnect the pins on the circuit blocks. Before discussing further, it would be prudent to discuss where does Routing actually fit in the Physical Design flow.

After Synthesis (the conversion of RTL to gate-level netlist), the blocks and the instances are Placed, which, to some extent, is governed by the Floorplan. After Placement, Clock Tree is synthesized followed by Routing of the signal nets. The following flow chart summarizes the Physical Design Flow.

Objectives of the Routing Process:

• To determine the necessary wiring, e.g., net topologies and specific routing segments, to connect these cells while respecting constraints like design rules.
• To Optimize routing objectives, e.g., minimizing total wire length and maximizing timing slack.

Routing is further divided into many subtypes:

• Global Routing: It defines the routing regions and generates a tentative route for each net. Each net is assigned to a set of routing regions. However, it does not specify the actual layout of wires and it not sensitive to DRV violations.

• Detailed Routing: For each routing region (defined during Global Routing), each net passing through that region is assigned to particular routing tracks. The actual layout of wires is specified. It also tries to fix all DRV violations in the design.

Puzzle: Identify the Issue with Circuit Topology

With the symbols having their usual meaning, identify the issue with this circuit topology.

[Hint]: Think from the timing perspective, and not the functional perspective.

You may answer the following:

• Issue with the topology.
• And in which kind of timing violation will the issue manifest itself while timing analysis.
• Possible modification(s) to solve the issue.

Clock Gating Integrated Cell

In the post, Clock Gating, we discussed the need for Clock Gating for Low Power Design Implementation. Clock being the highest frequency toggling signal contributes maximum towards the dynamic power consumption in the SoC even when the flops that are being fed by the clock are not changing their state. So, it is practical to gate the clock from reaching the set of registers or maybe some block in a design to save on the dynamic power consumption.

 You can relate it to the Standy mode in your PCs. In standy mode, only a sub-system of your entire SoC is working. Hence to save on the power consumption, one can employ clock gating. (Or maybe some other power saving methods, that we will discuss later).

Instead of using an AND or an OR gate for clock gating which is vulnerable to glitchy output, design engineers prefer to use the Clock Gating Integrated Cell (CGIC) to completely obviate the problem. Here's the circuit of a CGIC:

As evident from the above waveforms, if enable EN of the CGIC is logic-1, CGIC passes on the clock at the output without any glitch. And if EN is at logic-0, the outpiut is gated, i.e. no clock at the output and hence saving on the dynamic power consumption in the device.

Electrostatic Discharge vs Electromigration

Electrostatic Discharge and Electromigration might sound similar, but refer to different physical phenomenon. I would try to explain the difference between the two.

Electrostatic Discharge (ESD) is the large amount of current flow between any two points when a large (usually momentarily) potential difference is applied across those two points. In semiconductor terms, let's say you by some means a large potential is applied on the Gate of the MOS device, then a large current tend to flow through the gate and this in turn may disrupt the Silicon dioxide of the transistor. As you are aware this this silicon dioxide controls the important parameters like the threshold voltage (Vt) of the transistor, any physical damage would render the functionality of the entire device capricious.

To give you a general perspective: 

• The semiconductor industry incurs losses worth millions of dollars just due to ESD and therefore while shipping the parts, each and every IC is packed with utmost care and insulated from the outside world. 
• Also, while working in the labs in research centers or universities, or corporate, care is taken to obviate any excess potential from getting accumulated on any lab material. There's a separate ground for every device, which may be as small as a metallic needle. Even back in my college days, our professor used to admonish us for touching the pins of any IC with bare hands because sufficient potential can get accumulated on our body, specially, our extremities.

Note that ESD is a single time event. It can occur maybe while shipping, maybe while you are beginning to use the device or maybe when you are using that device.

Electromigration (EM): Let's say a device is operating over a long period of time. And there are certain regions in the device, where the current density is pretty high. These electrons have the propensity to displace the atoms of the device and this might create voids in certain regions and hillocks in other regions.

Timing: Basics

In a few earlier posts, we have already mentioned timing. It's time to discuss it formally.

Timing is a constraint that must be met so that the design functions the way it was meant to.

• What will happen if the timing constraints are met?
  You can be pretty sure that the device will function correctly at the frequency that was intended.
• What will happen if the timing constraints are not met?
  Device will not function correctly at the intended frequency. And it might or might not function at a slower frequency.

Pretty confusing? Don't worry. Read on.

Consider the following digital circuit. Two rise-edge triggered flops a and b, fed by a clock signal CLK, talking to each other. Output of Flop a after being processed by combinatorial logic Comb is reaching the input of Flop b.

How does the above circuit work? Consider the two waveforms which are the clock signals at flop a and b respectively. Flop a samples the input data IN at rising clock edge 1a and this data is captured by Flop b at the clock edge 2b. Similarly, data sampled and launched by the flop a at clock edge 2a is captured by flop b at 3b. 

As long as this launching and capturing relationship is maintained correctly, our timing constraint is also met and device would function perfectly fine! But the question: What actually is this timing constraint?

The data launched at edge 1a has to do undergo the following delays before it reaches the input of flop b.

Clock to q delay of Flop a and delay of the combinatorial logic Comb. 

And it should reach the input of flop b a at least some time before the edge 2b reaches the clock pin of Flop b. This time is called Setup Time. 

Also, we have to make sure that the data launched by Flop a at clock edge 1a is not captured by Flop b at clock edge 1b (it needs to be captured at 2b). So, the data must reach the flop b at least some time after clock edge 1b reaches Flop b. This time is called Hold Time.

Read the above two lines again. 

Same would be the relationship for other edges. Setup checks: 2a-3b; 3a-4b. Hold checks: 2a-2b; 3a-3b and so on.

Setup and Hold are the bread and butter of every backend design engineer. But why should the data reach some time before or after some clock edge? Where do these times come from? What exactly is the origin of setup and hold times? I do not mean any disrespect, but the answer to this question can puzzle even an experienced design engineer and I assure you that we will take this up in detail very soon.

For now, convince yourself that:

• Setup is a next-cycle check while hold is the same cycle check.
• Setup is dependent on the period (and hence frequency) at which your flip-flops are clocked while hold checks are frequency independent.

A direct ramification of the above statement is that setup violations can be fixed by lowering the operating frequency of the design. But hold violations cannot be fixed that way! I shall explain the Origin of Setup and Hold times soon. Also, I would like to take up some examples that would corroborate the concepts that I explained in this post.

Puzzle: Clock Transition

In the post Factors Affecting Delays of Standard Cells, we talked about the clock transition and the way it impacts setup and hold times.

While building our clock tree we ensure that clock transition is as low as possible. 

If clock transition or the slew at clock tree buffers were bad, apart from the penalty on hold time, what other deteriorating impact would it have on the design?

Factors Affecting Delays of Standard Cells

In this post, we would talk about the factors that affect the delays of standard cells. Before starting with the discussion, it would be prudent to discuss what is meant by Timing Arcs:

Timing Arcs: A timing arc represents the direction of the signal flow from usually an input to an output. They may be combinational or sequential. Combinational arcs represent the signal flow in combinatorial cells like AND, NAND, OR gates. Sequential arcs represents the signal flow in Flip Flops and they usually have a control signal like CLOCK associated with them. Third type that is closely related to sequential arcs are the setup and hold arcs. They represent the setup and hold requirements and in general, do not represent any signal flow. 

The information about these timing arcs come from the timing library (.lib) files.

Let's turn our attention back to delays.

Consider an AND gate. As discussed above, A to Z is a combinational timing arc. The delay of this arc is picked up from the .lib. This .lib is then read by the timing tools in timing reports.

This delay depends on primarily 2 factors:

1. The input slew or the transition at A pin.

2. The output load or the capacitance at the Z pin.

Note that the output load is the sum total of the input capacitance of the cells connected to the node Z and also the net capacitance of all such nodes.

Output Load = Input Cap of all cells at the fan-out of Z + Total net capacitance of the nets connected to node Z.

Delay is directly proportional to the input transition and the output load.
1. More is the output cap, more time the cell would require to charge/discharge that capacitance. And hence,  delays would be more.
2. More is the input transition, more time the cell would require to change the output after processing the input value.

You would note that explanation behind delays just boil down to charging/discharging of the capacitors!! Once you befriend them, you would be able to deduce half the concepts intuitively. 

We are now set to discuss the delays of timing arcs of a flip-flop.

1. Clock-to-Q delay: As expected, it depends upon the clock transition and the load at the output Q. It may sound surprising, but clock-to-q delay does not depend upon the transition at the D input.

2. Setup and Hold time: Setup and Hold time depend upon the transition value at clock pin and transition value at D pin. It does not depend on the output load.

Some surprises might be yet to unfold. Read on.
1. Clock-to-q delay is directly proportional to the clock transition and the output cap at Q.

2. Setup time is directly proportional to input transition at D and inversely proportional to the clock transition. Recall the definition of setup time. More is the clock transition time, more time you are allowing for the input at D to settle setup-time before the clock transition.

3. Hold time is inversely proportional to input transition at D and directly proportional to the clock transition. Again, recall the definition of hold time. More is the clock transition time, greater is the possibility that the D input might change in the hold window after clock transition.

I hope I was able to explain this stuff clearly. In case of any doubts, please feel free to post them here.

PVTs and How They Impact Timing

PVT is acronym for Process-Voltage-Temperature.

PVTs model variations in Process, Voltage and Temperature. There's other term OCV which refers to On-Chip Variation. PVTs model inter-chip variations while OCVs model intra-chip variations. 

We'll talk about OCVs in some other post.

Let's talk about PVTs in detail:

1) Process: You must have heard people talking in terms of process values like 90nm, 65nm, 45nm and other technology nodes. These values are characteristic of any technology and represents the length between the Source and Drain of a MOS transistor that you might have studied in your under-grad courses. While manufacturing any die, it has been seen that the dies that are present at the center are pretty accurate in their process values. But the ones lying on the periphery tend to deviate from this process value. The deviation is not big, but can have significant impact on timing.

Recall from your undergrad courses the following formula for current flowing in a MOS transistor:

                                             

L represents the process value. For same temperature and voltage values, current for 45nm process would be more than current for 65nm process.

More is the current, faster is the charging/discharging of capacitors. And this means, delays are less.

2) Voltage: The voltage that any semiconductor chip works upon is given from outside. Recall while working on breadboards in your labs, you used to connect a 5V supply to the Vcc pin of your IC. Modern chips work on very less voltage than that. Typically around 1V-1.2V.

This voltage must be the output of either a DC source or maybe the output of some voltage regulator. The output voltage of voltage regulator might not be a constant over a period of time. Let's say, you expected your voltage regulator to give 1.2V, but after 4 years, it's voltage dropped down to 1.08V or increased up to 1.32V. So, you gotta make sure your chip is working well between 1.08 and 1.32V!!

This is where the need to model Voltage variations come into picture.

From the same equation as above, it can be seen that more is the voltage, more is the current. And hence, delays are less.

3) Temperature: The ambient temperature also impacts the timing. Let's say you are working on a gadget in Siachen glacier where temperature can drop down to -40 degrees centigrade in winters and you expect your device to be working fine. Or maybe you are in Sahara desert, where ambient temperature is +50 degrees and your car engine temperature is +150 degrees and again you expect your chip to working fine. While designing, therefore, STA engineers need to make sure that their chip will function correctly in the temperatures between -40 to +150 degrees.

Higher is the temperature, more is the collision rate of electrons within the device. This increased collision rate forbids other electrons in the periphery to move. Since electron movement is responsible for current flowing in the device, current would decrease with increase in temperature. Therefore, delays are normally more at higher temperatures.

For technology nodes below 65nm, there's a phenomenon called TEMPERATURE INVERSION, where delays tend to increase with decreasing temperature. We shall talk about the same later. Don't get confused with it here.

WORST PVT: Process worst-Voltage min- Temperature-max

BEST PVT:  Process best-Voltage max- Temperature-min

WORST COLD PVT: Process worst-Voltage min-Temperature min

BEST HOT: Process best-Voltage max-Temperature max

STA engineers are responsible for closing the timing ( i.e. setup and hold ) at all these PVT corners.

So, next time you hear an STA engineer cribbing about his timing status across multiple PVTs, please show him some empathy!

Some related topics that we would discuss in upcoming posts:
1) On-Chip Variations and how they differ from PVT.
2) Temperature Inversion.
3) Factors affecting delays of standard cells.

Stay tuned for updates.