Clock to an SoC is like blood to a human body. Just the way blood flows to each and every part of the body and regulates metabolism, clock reaches each and every sequential device and controls the digital events inside the SoC. There are many terms which modern designers use in relation to the clock and while building the Clock Tree, the backend team carefully monitors these. Let's have a look at them.
- Clock Latency: Clock Latency is the general term for the delay that the clock signal takes between any two points. It can be from source (PLL) to the sink pin (Clock Pin) of registers or between any two intermediate points. Note that it is a general term and you need to know the context before making any guess about what is exactly meant when someone mentions clock latency.
- Source Insertion Delay: This refers to the clock delay from the clock origin point, which could be the PLL or maybe the IRC (Internal Reference Clock) to the clock definition point.
- Network Insertion Delay: This refers to the clock delay from the clock definition point to the sink pin of the registers.
Consider a hierarchical design where we have multiple people working on multiple partitions or the sub-modules. So, the tool would be oblivious about the "top" or any logic outside the block. The block owner would define a clock at the port of the block (as shown below). And carry out the physical design activities. He would only see the Network Insertion Delay and can only model the Source Insertion Delay for the block.
Having discusses the latency, we have now focus our attention to another important clock parameter: The Skew.
We discusses the concept of skew and it's implication on timing in the post: Clock Skew: Implication on Timing. It would be prudent to go through that post before proceeding further. We shall now take the meaning of terms: Global Skew and Local Skew.
- Local Skew is the skew between any two related flops. By related we mean that the flops exist in the fan-in or fan-out cone of each other.
- Global Skew is the skew between any two non-related flops in the design. By non-related we mean that the two flops do not exist in the fan-out or fan-in cone of each other and hence are in a way mutually exclusive.
In the next post we would discuss the implications of big clock latency on the timing. Please feel free to post your thoughts at my<dot>personal<dot>log<at>gmail<dot>com.
could you please elaborate on the relation between insertion delay and skew ?? is there any tradeoff between the two ?
ReplyDeleteYou brought up a very important point here. Ideally, skew and insertion delay are mutually exclusive.
DeleteHowever, while timing analysis STA team often use derates. (Click here to know more about OCV derates: http://vlsi-soc.blogspot.in/#!/2013/03/ocv-vs-pvt.html). It means that cells in the clock path would be derated. Greater insertion delay would typically mean, greater probability of variation. And hence, skew might increase and it may become a laborious task fixing the timing. Therefore, it is often desired to have maximum path between launch and capture as "common" to nullify the Common Path Pessimism.
Let me know if this needs further clarification.
Thanks!
1) How do you comeup with a skew and insertion delay target numbers to your block? will you consider source latency (fullchip cts ID to your block) while deciding the target?
Delete2) Among Global skew & Loacal skew, which skew is most important?
It would depend upon the maximum distance a clock signal is supposed to travel from the clock source to the sink pins, it would depend on the fanout (as in the number of sequentials) driven by the clock signal, the clock frequency, the technology, the OCV margins for that technology (which would in turn be governed by the application, maturity of that technology:: Refer to the post on OCVs).
DeleteGlobal skew might give a good idea about the overall placement of the sequentials, and the reason why some sequentials have higher latency than other sequentials (hence cauing higher global skew). One might want to tune their placement recipe a bit, because more latency for some sequentials would also mean higher clock power, area etc. Local skew makes more sense from timing standpoint, and if local skew gets messed up, designers would be able to detect that anomaly pretty quickly while checking their timing violations and the design QoR.
Regards,
Naman
Hi, If I had to engineer the arrival time of the clock at each each flipflop what command can be used in IC Compiler
ReplyDeleteTry using:
Deletereport_clock_timing -type latency -from (clock_source) -to (sink_pin_of_FF).
set_clock_tree_exceptions -float_pins [get_pins {flip-flop1/CLK ...}] delay_value
ReplyDeleteThe float pin delay values can be either positive or negative, depending on your timing requirements. To increase the path delay to a pin, specify a negative float pin delay. To decrease the path delay to a pin, specify a positive float pin delay. This is also known as macro-modelling/startpoint-endpoint skewing technique.
In IC Compiler 2 , this command is replaced by set_clock_balance_points
Hi PD people, how do I come up with delay_value , equivalently in ICC2 set_clock_balance_points -delay $delay , when I have to balance certain clk pins explicitly with other sinks?
DeleteCan global skew be of importance during hold anlaysis of scan chains?
ReplyDelete