April 21, 2013

Puzzle: DFT Shift Frequency

It is a well known fact that DFT Shifting is done at a slower frequency. Well, I'm gonna list down some cons against this. You'll have to tell the pros!

  • Lower is the frequency, greater is the test time. In modern SoCs, tester cost  (which is directly proportional to the tester time) accounts for roughly 40% of the selling price of a single chip. It would be pragmatic to decrease the test time by increasing the frequency. No?
  • Increasing the frequency would not pose any timing issue. Because, hold would anyway be met (Hold check is independent of frequency). And setup would never be in the critical path considering the fact that scan chains only involve direct path from output of a flop to scan input pin of the next flop, devoid of any logic.

Then why not test at a higher frequency, which is at least closer to the functional frequency? What could possibly be the reason for testing at slower frequency?

25 comments:

  1. I am curious to know why not test at a higher frequency, which is either matching or closer to the functional frequency? And what are the limiting factors for testing at slower frequency?

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    1. Hello there! I'll surely answer it tomorrow, but before answering I would like you to think from the perspective of power consumption.

      Thanks!

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    2. Unlike functional mode, where different paths have varying combinational logic between any two registers, in shift mode, there is absolutely no logic at all! Hence, all the flops tend to switch at the same time. Imagine all the flops switching at the same time. The peak power consumption which is directly proportional to the switching frequency, would shoot up, maybe upto the point that the IC might catch fire!!

      Also, in functional mode, the entire SoC does not function simultaneously. Depending on use-case, some portions will either not work, or work in tandem.

      You might argue here, that one can run shift the same way, i.e. different parts in tandem. But that would mean, higher test times that we intended to reduce by increasing the shift frequency in the first place.

      Please let me know if you didn't get any part of it! :)

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    3. thanks for clear and straight explanation.

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    4. Hi Sunil.

      I am glad you liked it! Check out other puzzles as well, especially the one on "Stuck-At Faults".

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    5. Nice Explaination.. Thanks

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    6. Suppose I have a power controller (like EDT power controller).
      In such a situation what is the limitation?

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    7. Hi Naman, could you please explain the relationship between scan shift/capture and power consumption

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    8. Hi Redouane,

      That's a very good question, and could well be a separate post.
      We need to understand power from two perspective- the peak power dissipation and the average power dissipation. While shifting, all the flip-flops toggle right at the active clock edge unlike functional mode where some parts might be disable (clock gated), or perhaps power gated. Hence, during shift mode, DFX engineers would primarily be concerned about peak power dissipation which can potentially harm the chip if the shift frequency is too high. The motivation for higher shift frequency is lower test time.

      However, for capture mode, I'm not really concerned about capture frequency because it's just one cycle! I can have the capture frequency as low as possible and not worry about test time. Therefore, power is never really a concern for capture mode.

      For Atspeed mode, both peak and average power make a difference. Peak power dissipation can result in voltage droop, and subsequent malfunction. The reason why I'd be concerned about average power in atspeed mode would be because atspeed is run at the functional frequency, which would certainly be higher than the shift or the stuckat frequency.

      I hope my answer made sense. Feel free to get back in case you need some more clarification, or you have some comments.

      Thanks,
      Naman

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    9. Hi Naman,

      I didn't understand about atspeed mode. Could you please explain it some what clearly.

      Thanks....

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  2. Another limitation is from tester. Typically shift clock is from tester, which has very limited high-speed pins connected to the chip. Moreover, your design should have high-speed pad in order to load data from tester, which is also very expensive.

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    1. Right. That's a good point. For shifting, I'll need to give the test clock from outside and it would be limited by what the maximum frequency my pads can support.

      For other DFT modes like Atspeed, the clock would be generated internally using the PLL.

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  3. Hi,
    Now days PADs run in GHz also high end testers can generate the scan freq at higher freq what is the constraint in that?

    and alter your shift clock in such a way that all clock will not be seen at time just scatter-[delay it in different paths ] it , such that you will not hit the peak power issue

    -Ram ram

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    1. Hi Ram,

      Yes, if all the paths have different delays, peak power won't be a problem. But in shift mode, there's no combinational logic in the data path, except for hold buffers. Assuming a worst case skew window of let's say X ps, most of the flops would toggle in this window, resulting in a peak power issue during this window. I agree with you that peak power issue would be contingent upon the delay.

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  4. For finding stuck at faults in scan chain y time period of shifting and capturing cycle are equal?

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    1. Hi Bharath,

      Time period of shifting and capturing cycle are not equal. Shifting clock frequency would typically be in the range of few tens of MHz. While capturing frequency has to be much slower, and would typically be 1-2 MHz.

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    2. i am not agree. capture frequency is almost equal to functional frequency which is lesser than shifting frequency

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  5. Hi Naman,
    Whether all flops switch at the same time or not - isnt this dependent on data pattern ? I didnt quite understand when you "all flops switch at the same time."

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    1. Hi Niketh,

      It certainly is! For peak power, I need to consider the worst case data pattern which could perhaps be: 101010101... Even with this pattern, the time at which flops would switch would depend on the data path delay comprising or hold buffers, and the skew between any two flops in the scan chain. But the peak power would still be more as compared to the functional mode.

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  6. good data points. thank you.

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