April 19, 2013

Puzzle: Stuck-At Fault

A brief introduction to Stuck-At Faults was given in the post: Design for Testability: Need for Modern VLSI Design. You might want to go through it first. Anyway, as the name suggests, stuck-at faults manifest themselves if any particular node  in the design is "stuck" at either 0 or 1. A plausible explanation for stuck-at-0 (SA0) might be that the particuular node on question has somehow been shorted to Ground (GND at 0V) . Similarly, a node might be Stuck-At-1 (SA1) if let's say it is somehow shorted to the VDD (at logic 1).

In order to detect a stuck-at-0 fault, we would try to excite that node to the opposite value, i.e. 1 and try and see if we are able to achieve that. If we are able to do so, we can safely say that the node in question in NOT stuck-at-0. And vice-versa.

In the below question, we intend to check the node X for a stuck-at-0 fault. Can you tell what input vector (A,B,C) would be need to give to do so?

1. The vector will be (1,0,0)

2. If we want to check for stuck@0 @ node X, then we have to see to it that the node is forced to 1, this can be done if A=1, B=0 & C=0.

1. Yes, that is correct! Thanks for answering the question!

Regards,
Vipul

3. Hey, thanks, man! It feels great to hear that!

I read about JTAG and worked on it some time back. I'll surely try to revisit the concept and come up with a blog post soon. Stay tuned!

Thanks, again!

Regards,
Naman

3. 010,100,101

4. Hello Anonymous, the test vector 010 and 101 won't be able to check stuck-at-0 fault because the output at testing node will be 0. but 100 will work with no problem.

5. the vector should be 1,0,0 to force the Node X to 1, so if we get 0 at this Node, then we can say that it's a SA-0-

6. How would we check Stuck-At faults if it occurs at the input of the gate? Say I have a Stuck-At fault at "A" in the figure above. How would I check that?

1. A=0, B=0, C=0 tests that fault.

2. *Assuming we want to test SA-1 for A.
We set it to 0 and try to propagate this to the output.

At the first XOR, B=0 or B=1 will allow A to propagate both its cases to output of the XOR. Then next stage and gate is simpler. The other input must be 1 for the signal to go through the and gate.

This allows us to back track the constant 1 signal so we get information on B and C.

When is NOR 1? When both inputs are 0.

-Vaibhav

7. Hello Everyone,
In my design suppose if scan frequency and function frequency are given same. So do I want to test Transition delay Fault ? .