May 04, 2013

Combinational Loops

You would often hear backend engineers remonstrating the frontend design folks on the presence of combinational loops in the design. But why do they create such a hue and cry? What possibly could one or maybe few combinational loops do? Well, potentially, they can render the entire functionality of the SoC haywire and not taken care off. And some combinational loops, on the other hand, are indispensable for the evolution of a particular technology. We'll see how and why.

A combo loop is structure which is formed by a signal starting from an input of a combinational gate, after passing through one or more combinational gate, reaches the same combo gate from which it started without encountering any sequential element in between.

Here's what a generalized combo loop looks like:

  • Unstable Loops: Let's start with a basic combo loop that you must have studied in your academics or at least heard about it. The reverend Ring Oscillator. It is an inveterate fallacy that a ring oscillator can be used to make a clock generating circuit. Trust me, clock generating or even divider circuits, for that matter, are not as simple as the ring oscillator shown below. 

Of what use could this simple circuit be? Well, if we can control any one input of any of the three inverters shown here, we can know the delay of an inverter which is often the first cell to be characterized in any technology. Moreover, test structures like these also help the foundry guys in determining the manufacturing process of a particular chip whether it was WCS or BCS.
  • Stable Loops: Here's an example of a stable loop consisting of an OR gate. Note that, as soon as the free input receives a logic 1, the output goes to 1. And same signal is conveyed back to the another input, and the loop is stable or rather stuck-at-1.

Note that stable loops would not pose problems of copious dynamic power consumption. But such a loops pose headaches to DFT teams. Recall from the post: Two Pillars of DFT: Controllability & Observability, we talked about how stuck-at faults are simulated and detected. If such a loop would be present in the design, any stuck-at faults in the vicinity of this gate cannot be observed, and hence DFT team would lose their stuck-at coverage by a considerable amount!!

STA Concerns: We started this post with a preamble talking about backend engineers repining the frontend engineers. How would a backend engineer be affected by a combo loop? Here's how.

Recall from the post: Factors Affecting Delays of Standard Cells that the delay and output slew of any standard cell depends on the input slew and output load. The below figure shows one such example, where slew can keep on degrading indefinitely, and would ultimately impact the timing and more importantly the power consumption of the SoC.

To sum up, combo loops must be avoided in all SoCs except for special circumstances like ring oscillator circuit can be employed for testing the characteristics of the SoC.


  1. Hi,
    I have a doubt.
    What is the impact of combinational loops in CTS?

  2. Combinational loop impacts the backend functionas like STA, CTS indirectly. And it is mainly because of the interpretation of EDA Tools. Typically, EDA tools try to break the combo loops by arbitrarily chosen cut points. Might be fine, but more often than not, it breaks it in a way that the clock to a majority of flops would be cut off. Hence, you would see many flops in your design as unclocked. Here, it becomes important to understand the architecture and proper case settings or identifying appropriate cut points.

    Hope I was able to answer it correctly. :)

    1. thanks!!!

    2. Hi Palindrome,

      I did not understand "it breaks it in a way that the clock to a majority of flops would be cut off.". Why would a combo loop in the data path cut off the clock ( unless it's somehow fiddling with clock gating enable ). I was of the opinion that the tool might break the loop at random points thereby masking actual critical paths.

  3. Sometimes there are combinational loops seen by timing tool but algorithmically no loops exists. In such situations where the EDA tool breaks the loop,certain paths will never be timed. In such situations , the RTL has to be redesigned I guess....

  4. Dear, Palindrome,

    What kind o verilog construct will generate combinational Loops in synthesis?


  5. always_comb a = b ? c : a
    will lead to a combo loop!

  6. How to verify feedback loops in the design with functional verification