IR Drop Analysis

Just yesterday, I got a question from one of our readers Lakshman Yandapalli. I thought it would be nice to write a blog post for you all!

Let's start with some background as to what indeed is the IR drop analysis.

When we talk about standard cells, we usually talk about the logical pins, let's say, A and B for the inputs and Z for outputs. What we do miss stating explicitly are the power/ground pins: the VDD and the VSS. These connections are usually implicit from the context (unless of course if you have a Muti-voltage design! Let's save this story for some other post).

IR drop is the voltage drop in the metal wires consituting the power grid before it reaches the VDD pins of the standard cells. Why do we bother about the voltage? Because the speed of the standard cell (the propagation delay) would be directly proportional to the VDD value. Higher VDD would mean faster cell, or lower propagation delay.

Now imagine that your SoC has a nominal voltage of 1V, and you closed your setup timing assuming the ideal 1V libraries. However, the IR drop of 40mV came into picture after you built the power grid, and the voltage is no longer 1V, let's say it is 0.96V. Now, with V = 0.96V, the delays of standard cells would be higher and you might see an increase in your setup-time violations!

Let's look into the factors that could cause this IR drop and how can we mitigate those factors, and what should our sign-off corners be to make sure no failures post-silicon!

While considering IR drop, you'd be concerned with two factors:

1. Static IR Drop: Dependent on the RC of the power grid connecting the power supply to the respective standard cells.

It is ALWAYS desirable to create the POWER GRID in higher metal layers. Higher metal layers would mean more wide wires, and hence would mean lower resistance. Lower resistance would mean that the IR drop would be lower, and hence lesser impact on setup-timing. 

Capacitance of metal wires would be the combination of ground and the coupling capacitance. If for some reason, you feel that the capacitance is too large, and it is indeed the reason for IR drop, it could either be because 

• Long wire length: Resulting in higher wire cap. 
• High fan-out of the net: Resulting in higher load-cap, or perhaps 
• High routing congestion in a particular area resulting in high coupling capacitance with the neighboring nets.

Now, how to mitigate the problem? You can try splitting the net so that the fan-out gets distributed (pretty much similar to building a clock tree), you can split the long wire by placing appropriate power bumps. Or you can also analyze the congestion and space the wires apart to reduce coupling capacitance!

Update: 

Simple equation representing the static IR drop would be the following:

Vstatic_drop = Iavg x Rwire

2. Dynamic IR Drop: Dependent on the switching activity of the standard cells themselves.
Switching activity of standard cells also contributes significantly to the IR drop, also known as the Dynamic IR drop. Higher would be the switching activity, in a given region, there'll be an increased demand for current from the power supply. More is the current, more would be the IR drop (which is essentially Current times the wore resistance!).
If you ever come across such a use case, you might want to space the standard cells apart so that the burden on a given bump to feed many standard cells which have high switching activity would be mitigated. 
Dynamic IR Drop is also sometimes referred to by the term of Voltage "Droop".
Update: Dynamic IR drop is contingent upon the current drawn by the standard cells, and that brings in a time-dependent variation of current into picture. Dynamic IR drop is represented by the equation:

Vdynamic_drop = L (di/dt)

Now that we have a fair understanding of IR Drop analysis, let's talk about the PVT/RC corners where one should analysis IR drop in their design.

Let's start with the RC corner.

1. RC Corner: The RC corner where the physical design engineers should analyze for IR drop would be the case when the RC product is worst. And that would indeed be the (RC)max corner, also referred to as the RCWorst corner.

2. PVT Conditions: PVT conditions would typically impact the standard cells. For IR drop analysis we would be concerned about the case where we expect the highest switching activity for standard cells. That would be the FF corner, High voltage, and high temperature.

High temperature might seem an anomaly, but higher temperature would mean higher wire resistance as well, and hence higher RC!

Last comment about IR drop analysis. It also makes sense to run IR drop analysis for the worst case setup timing check because IR drop would most probably impact only setup timing. So, designers may want to run the IR drop analysis for the RCWorst, High Temperature, SS slow and low voltage. But typically it is not done because the low voltage corner is usually already guard-banded to account for the IR drop. So, running IR drop analysis on the low voltage corner would be overly pessimistic! 

Self Gated Flip-Flop

Hey folks!

Just yesterday, I was wondering if it's possible to come up with a self gated flip-flop architecture which could be used to extreme low-power applications. As soon as I designed the flip-flop and satisfied myself that it seemed to be working well on paper, I was ecstatic! However, that was short-lived because a prior art search revealed that someone had already designed a pretty similar structure 2 years back!

But since I found it cool, I'm tempted to share it with the readers here. Let's start with the motivation for such a flip-flop.

There may be applications in which certain flip-flops of the design may toggle states quite infrequently. Now, it's a well known fact that even though a flip-flop is not switching states, it will continue to dissipate dynamic power internally as long as the clock is constantly switching states. And there's also a well-known, exalted solution of clock gating! But clock gating is not always a viable solution. Let's look at the reasons when and why clock gating may not be a viable solution:

Clock Gating Integrated Cell

• Clock Gating is usually performed by using a clock gating integrated cell, which essentially comprises of a latch and an AND gate. Latch itself is a sequential element, and logically half of the flip-flop, and physically takes up around 60-65% of the flip-flop area. Coupled with an AND gate, the internal switching activity of the clock gating cell would result in significant standby power dissipation.
• Adding a clock gating cell makes sense only if there are a bunch of flip-flops to be clock gated. That is basically to offset the extra overhead of power dissipation within a clock gating cell.
• Clock Gating cell will also have additional logic to control it's enable signal, leading to more power dissipation, however, this component is not really significant in most of the cases.

All the above reasons point for need of an effective strategy for a fine-grained clock gating technique without worrying about any additional overheads one might incur in doing so. That way a self-gated flip-flop might come to our rescue and would help in saving that extra milli- or perhaps micro-watts of power! Pretty cool, no! ;)

Architecture:

What I thought was: flip-flop would have a state either 0 or a 1. And these are the only two states that one ever needs to worry about. And this is best accomplished by a toggle flop.

Toggle Flop

Now, let's say initially flip-flop was reset to 0 and D was 0. The flop should be self gated. And as soon as D goes to 1, the flip-flop should TOGGLE, and stay at 1 as long as D stays as 1. So, we need the following components: a toggle flop; a XOR between D, Q; and a clock gating logic (either an AND or an OR gate).

Connections are pretty intuitive as shown as follows:

Implementing XOR is simple, and can be accomplished by using 8 transistors plus inverters. NOR gate would need 4 additional transistors. So, using just 12 extra transistors on top of the existing flip-flop circuit, you get a self-gated flip-flop with minimal dynamic power! How's that for a circuit?!

Self-Gated FF

It would be prudent to add the name of the patent/publication that I eventually found in the references, so that nobody accuses me of plagiarism! :D
Reference: 

• Low Power Toggle latch-based flip flop including integrated clock gating circuit: US 20150200652A1.

Hold Time Violations

How often has someone asked you how to fix setup time violations?! And how often have you replied with many techniques ranging from cell upsizing, to logical retiming. From Vt swapping to utilizing useful clock skew or perhaps even reduction in the clock frequency?

And how often someone has trapped you for the asking the impact of clock frequency on the hold time!

Let's imagine a scenario. You designed a chip, and it's been manufactured. You discovered that there's one hold time violation and let's say, the slack is -10ps. Well, logical answer would be to throw that chip away since hold time cannot be met by tweaking the clock frequency. But it it were that simple, I wouldn't have asked this question! :P

Now, think a little. And answer what all "engineering tweaks" you can do in order to make the chip work, or I should say to try and make the chip work?

I expect a healthy discourse on this question, and I'm sure even I would end up learning a few things which I might not have appreciated till now. I request you to enlighten me with your thoughts.

Thanks! :)

Puzzle: Logical Restructuring

Can you comment on the functionality of the below circuit?

Using the concept of bubble shifting, can you optimize the above circuit to reduce its area? Consider all gates to be implemented in standard CMOS technology, and assume that area is directly proportional to the number of transistors used.

You may also compute the percentage area reduction as a result of bubble shifting by counting the number of transistors in the optimized circuit.

Puzzle: Stuck-at Fault

Around 2.5 years back, I had posted a Puzzle: Stuck-At Fault on this blog where I had asked to find the input vector to detect a particular stuck-at fault in a given circuit. This puzzle is exactly the same problem, but with a more complex circuit.

Assuming a SINGLE STUCK-AT FAULT MODEL, could you please help me with the input vector to detect:

1. A Stuck-at-0 fault at node L.
2. A Stuck-at-1 fault at node L.

Please post your answers in the comment section below.

Channel Length vs Gate Length

Till a few months back, I assumed that channel length and gate length were same terms used interchangeably. However, one of the classes that I took at USC cleared this doubt and I'm very thankful to my professor for explaining the subtle difference between the two.

The figure above shows the cross-section of an NMOS with it's source, drain, gate. Let's talk about the difference between gate length, channel length and the diffusion length.

While fabricating a MOS device, typically the poly gate is grown first using the minimum feature size mask which is characteristic of a particular technology node. After this, the source and drain are formed by ion-implantation of Phosphorus (n+). This is referred to as self-aligned process. After ion-implantation, there is some side diffusion of the implanted ions because of which, the n+ region extends up to a small width below the gate. This is referred to as the diffusion length or the diffusion width. The effective distance between the drain and the source where the channel would eventually be formed and the actual length an electron would travel from source to drain is called the Effective Channel Length! I encourage you to read up more about the steps in CMOS Fabrication for better understanding. 

As evident from the above figure:

Channel Length = Gate Length - 2 x (Diffusion Length)

Well, that was theory! Now some practical discussion. :)

When we say that we have let's say a 28 nm technology node. Which of the above would be 28 nm? Well, it would be the GATE LENGTH! As pointed above, gate corresponds to the minimum feature size mask which is characteristic of a particular technology node!

Now, let's say, this NMOS is operating in the saturation regime, and there's no pinch off yet. If you wish to find the saturation current flowing through the device, you'll have to use the channel length in the formula for the drain current which is a quadratic function of the gate-to-source voltage. 

How do we find this channel length? For older technology nodes (like 250 nm), this diffusion used to be negligible as compared to the gate length. However, for advanced sub-micron technology nodes, the side diffusion length is typically 10% of the gate length. (Actual numbers may vary from one manufacturer to another). So, for 28 nm technology node, you might expect the actual channel length to be in the order of 20-22 nm.

Drain and the Source of MOS Transistors

How does one decide which terminal of the MOS Transistor is the Source and which terminal is the Drain?

While most of us are taught one basic rule in our introduction classes to the CMOS Transistor: The source of an NMOS is typically at the lowest potential while the source of a PMOS transistor is at the highest potential. 

While this rule is correct, there got to be a plausible technical explanation behind this nomenclature. In this post, I'll discuss that explanation.

First of all one must appreciate the fact that unlike BJT, MOSFET is a symmetric structure. By this, I mean that any terminal can act as drain or source depending upon the voltage applied on that particular terminal. In NMOS: Source is the terminal which is at the lowest potential. In PMOS, Source is the terminal with the highest potential. Now, the question arrives why did we choose to call a particular terminal as source or drain. Read on.

In NMOS, the majority charge carriers are the electrons. If you've followed the physics behind the transistor operation, you'd know that current in an NMOS flows from Drain to Source. Alternatively, electrons flow from the source to drain. Source is therefore the "reservoir" or "source" of electrons which get "drained" at the Drain! That's where the terminology comes from. Therefore, the source of electrons in an NMOS has to be connected to the lowest potential, that being the VSS. And Drain to the higher potential, which could perhaps be VDD.

In PMOS, the majority charge carriers are the holes. Holes will flow from higher potential to a lower potential. Higher potential terminal would act as the "source" of holes. That would therefore be VDD. These holes would get "drained" at a lower potential, which could perhaps be VSS. Therefore, for PMOS, higher potential terminal would be the Source, and lower potential terminal would be the drain!