Can you comment on the functionality of the below circuit?

Using the concept of bubble shifting, can you optimize the above circuit to reduce its area? Consider all gates to be implemented in standard CMOS technology, and assume that area is directly proportional to the number of transistors used.

You may also compute the percentage area reduction as a result of bubble shifting by counting the number of transistors in the optimized circuit.

The above logic checks whether any corresponding bit of buses a[7:0] and b[7:0] is logic one. It has 80 transistors(8*6 + 4*6 + 8).

ReplyDeleteIf we remove the 2-input OR gates and merge their function with 4-input OR gate, we will have 8-input OR gate. Now by bubble shifting, the 2-input AND gates will become 2-input NAND gate and 8-input OR gate will become 8-input NAND gate.

So the number of transistors in this optimized logic will be 48 (4*8 + 16).

%area reduction = 32/80 = 40%

Hello Kalpana Singla.

DeleteSorry for my nescience.

Could you please explane why 4OR element has only 8 transistors not 10? If understand correctly your calculation (8*6 + 4*6 + 8) 6 is 4NOR(NAND) + 2NOT. But what about 8 here?

Thank you in advance.

Hi Kalpana & Alexanser,

DeleteLet's forget about the minor oversight of the 4-input OR gate using 10 transistors instead of 8, as Kalpana mentioned..

That's a fantastic solution! You used the correct approach and satisfied all the constraints I had placed in the problem.

However, I'd just like to mention one small point: Typically, standard cell libraries don't have any gate with a fan-in of more than 4! So, typically, all you'd find is perhaps a 4-input NAND gate, or for that matter, a 4-input OR gate. Can you please modify your solution a bit?

Thanks again for posting the answer!

Regards,

Naman

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ReplyDeleteThis comment has been removed by the author.

DeleteReplace all the gates with NAND gate. Since it is CMOS logic.It would take 2tx/gate. In total 26tx are reduced.

ReplyDelete

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