Self Gated Flip-Flop

Hey folks!

Just yesterday, I was wondering if it's possible to come up with a self gated flip-flop architecture which could be used to extreme low-power applications. As soon as I designed the flip-flop and satisfied myself that it seemed to be working well on paper, I was ecstatic! However, that was short-lived because a prior art search revealed that someone had already designed a pretty similar structure 2 years back!

But since I found it cool, I'm tempted to share it with the readers here. Let's start with the motivation for such a flip-flop.

There may be applications in which certain flip-flops of the design may toggle states quite infrequently. Now, it's a well known fact that even though a flip-flop is not switching states, it will continue to dissipate dynamic power internally as long as the clock is constantly switching states. And there's also a well-known, exalted solution of clock gating! But clock gating is not always a viable solution. Let's look at the reasons when and why clock gating may not be a viable solution:

Clock Gating Integrated Cell

• Clock Gating is usually performed by using a clock gating integrated cell, which essentially comprises of a latch and an AND gate. Latch itself is a sequential element, and logically half of the flip-flop, and physically takes up around 60-65% of the flip-flop area. Coupled with an AND gate, the internal switching activity of the clock gating cell would result in significant standby power dissipation.
• Adding a clock gating cell makes sense only if there are a bunch of flip-flops to be clock gated. That is basically to offset the extra overhead of power dissipation within a clock gating cell.
• Clock Gating cell will also have additional logic to control it's enable signal, leading to more power dissipation, however, this component is not really significant in most of the cases.

All the above reasons point for need of an effective strategy for a fine-grained clock gating technique without worrying about any additional overheads one might incur in doing so. That way a self-gated flip-flop might come to our rescue and would help in saving that extra milli- or perhaps micro-watts of power! Pretty cool, no! ;)

Architecture:

What I thought was: flip-flop would have a state either 0 or a 1. And these are the only two states that one ever needs to worry about. And this is best accomplished by a toggle flop.

Toggle Flop

Now, let's say initially flip-flop was reset to 0 and D was 0. The flop should be self gated. And as soon as D goes to 1, the flip-flop should TOGGLE, and stay at 1 as long as D stays as 1. So, we need the following components: a toggle flop; a XOR between D, Q; and a clock gating logic (either an AND or an OR gate).

Connections are pretty intuitive as shown as follows:

Implementing XOR is simple, and can be accomplished by using 8 transistors plus inverters. NOR gate would need 4 additional transistors. So, using just 12 extra transistors on top of the existing flip-flop circuit, you get a self-gated flip-flop with minimal dynamic power! How's that for a circuit?!

Self-Gated FF

It would be prudent to add the name of the patent/publication that I eventually found in the references, so that nobody accuses me of plagiarism! :D
Reference: 

• Low Power Toggle latch-based flip flop including integrated clock gating circuit: US 20150200652A1.

Hold Time Violations

How often has someone asked you how to fix setup time violations?! And how often have you replied with many techniques ranging from cell upsizing, to logical retiming. From Vt swapping to utilizing useful clock skew or perhaps even reduction in the clock frequency?

And how often someone has trapped you for the asking the impact of clock frequency on the hold time!

Let's imagine a scenario. You designed a chip, and it's been manufactured. You discovered that there's one hold time violation and let's say, the slack is -10ps. Well, logical answer would be to throw that chip away since hold time cannot be met by tweaking the clock frequency. But it it were that simple, I wouldn't have asked this question! :P

Now, think a little. And answer what all "engineering tweaks" you can do in order to make the chip work, or I should say to try and make the chip work?

I expect a healthy discourse on this question, and I'm sure even I would end up learning a few things which I might not have appreciated till now. I request you to enlighten me with your thoughts.

Thanks! :)

Puzzle: Logical Restructuring

Can you comment on the functionality of the below circuit?

Using the concept of bubble shifting, can you optimize the above circuit to reduce its area? Consider all gates to be implemented in standard CMOS technology, and assume that area is directly proportional to the number of transistors used.

You may also compute the percentage area reduction as a result of bubble shifting by counting the number of transistors in the optimized circuit.

Puzzle: Stuck-at Fault

Around 2.5 years back, I had posted a Puzzle: Stuck-At Fault on this blog where I had asked to find the input vector to detect a particular stuck-at fault in a given circuit. This puzzle is exactly the same problem, but with a more complex circuit.

Assuming a SINGLE STUCK-AT FAULT MODEL, could you please help me with the input vector to detect:

1. A Stuck-at-0 fault at node L.
2. A Stuck-at-1 fault at node L.

Please post your answers in the comment section below.

Channel Length vs Gate Length

Till a few months back, I assumed that channel length and gate length were same terms used interchangeably. However, one of the classes that I took at USC cleared this doubt and I'm very thankful to my professor for explaining the subtle difference between the two.

The figure above shows the cross-section of an NMOS with it's source, drain, gate. Let's talk about the difference between gate length, channel length and the diffusion length.

While fabricating a MOS device, typically the poly gate is grown first using the minimum feature size mask which is characteristic of a particular technology node. After this, the source and drain are formed by ion-implantation of Phosphorus (n+). This is referred to as self-aligned process. After ion-implantation, there is some side diffusion of the implanted ions because of which, the n+ region extends up to a small width below the gate. This is referred to as the diffusion length or the diffusion width. The effective distance between the drain and the source where the channel would eventually be formed and the actual length an electron would travel from source to drain is called the Effective Channel Length! I encourage you to read up more about the steps in CMOS Fabrication for better understanding. 

As evident from the above figure:

Channel Length = Gate Length - 2 x (Diffusion Length)

Well, that was theory! Now some practical discussion. :)

When we say that we have let's say a 28 nm technology node. Which of the above would be 28 nm? Well, it would be the GATE LENGTH! As pointed above, gate corresponds to the minimum feature size mask which is characteristic of a particular technology node!

Now, let's say, this NMOS is operating in the saturation regime, and there's no pinch off yet. If you wish to find the saturation current flowing through the device, you'll have to use the channel length in the formula for the drain current which is a quadratic function of the gate-to-source voltage. 

How do we find this channel length? For older technology nodes (like 250 nm), this diffusion used to be negligible as compared to the gate length. However, for advanced sub-micron technology nodes, the side diffusion length is typically 10% of the gate length. (Actual numbers may vary from one manufacturer to another). So, for 28 nm technology node, you might expect the actual channel length to be in the order of 20-22 nm.

Drain and the Source of MOS Transistors

How does one decide which terminal of the MOS Transistor is the Source and which terminal is the Drain?

While most of us are taught one basic rule in our introduction classes to the CMOS Transistor: The source of an NMOS is typically at the lowest potential while the source of a PMOS transistor is at the highest potential. 

While this rule is correct, there got to be a plausible technical explanation behind this nomenclature. In this post, I'll discuss that explanation.

First of all one must appreciate the fact that unlike BJT, MOSFET is a symmetric structure. By this, I mean that any terminal can act as drain or source depending upon the voltage applied on that particular terminal. In NMOS: Source is the terminal which is at the lowest potential. In PMOS, Source is the terminal with the highest potential. Now, the question arrives why did we choose to call a particular terminal as source or drain. Read on.

In NMOS, the majority charge carriers are the electrons. If you've followed the physics behind the transistor operation, you'd know that current in an NMOS flows from Drain to Source. Alternatively, electrons flow from the source to drain. Source is therefore the "reservoir" or "source" of electrons which get "drained" at the Drain! That's where the terminology comes from. Therefore, the source of electrons in an NMOS has to be connected to the lowest potential, that being the VSS. And Drain to the higher potential, which could perhaps be VDD.

In PMOS, the majority charge carriers are the holes. Holes will flow from higher potential to a lower potential. Higher potential terminal would act as the "source" of holes. That would therefore be VDD. These holes would get "drained" at a lower potential, which could perhaps be VSS. Therefore, for PMOS, higher potential terminal would be the Source, and lower potential terminal would be the drain! 

The Timing Optimization Problem

Puzzle:

Tomorrow is the scheduled tape-out of your SoC. The target clock frequency for this SoC is 100 MHz (Time Period of 10 ns). However, there's only one setup violating path and you need to fix the timing by doing ECOs. Area is not a constraint.

Here's the circuit:

Points to note:

• My tape-out is tomorrow, I don't have the liberty of asking the RTL design team to change the architecture of the design.
• I have used the highest possible drive strength cells, and perhaps the lowest Vt flavor cells available in my standard cell library.
• There's no redundant logic in the path, it's been optimized well.
• I cannot add delay to the clock path of FF2 because doing so, the hold time of the scan chain connecting flops FF1 and FF2 would fail.

Please suggest ways to solve this timing violation. A rough image would be really helpful. I shall post my solution in a couple of days time.

Mike posted the correct answer, and I'll just add a figure explaining the solution: