February 05, 2017

Power Domain Crossings

With all the fuss about low power designs, the implementation of multiple power domains has gained significant traction in the past decade and they still play a critical role in designing the chips which are less power hungry. The use-cases have become more complicated and keeping up with the pace, the implementation techniques have become even more intricate! 

In this post I intend to talk about the motivation for power domains, draw a distinction between two commonly confused terms- the power domain and the voltage area, and some basics which can help the newbies lay a foundation of what to expect while implementing such designs.

As we've already discussed, the basic intention to create multiple power domains is to reduce the power consumption. But how does it help? Let's take a look. Let's say your design has three IPs- Alpha, Beta and Gamma. The Alpha IP is the heart of the design and it's basically the computation engine- think of something like the ALU or the Execution Unit. Beta IP does house-keeping jobs, mostly in the support role. While Gamma IP does all the "dirty"stuff- think of something like analog IPs like the Power Management Unit. Now, one important thing to appreciate here is that these three IPs serve different purposes, at different times with a distinct level of significance. 

Let's dig a little bit deeper into this. Aplha IP does the most important task, it is critical for performance and therefore should run at the highest possible clock frequencies and therefore burns a significant chunk of the overall power consumption. Beta IP is not needed that often, and neither does any critical work, nor does it all the time! Gamma IP does the significant task of managing the power supplies and therefore needs to be always-on!

Having delineated the expectations for each IP, now it's time to delve into some technical details that would be of particular interest to a physical design engineer and let's try and understand the rationale behind it. This time we shall start from Gamma IP. Gamma IP being the analog IP (or at best a mixed-signal IP) usually operates on high voltage because analog circuits are usually more susceptible to noise. Let's say Gamma IP operates on 3V. (Unrealistic number, when it comes to modern VLSI design, but I intend to give you a relative context! :)) Beta IP is a digital IP therefore it can operate on a lower voltage, let's say 1V in our chip and it would be a switchable IP, meaning that we can turn-off the power to this IP when it's not in use, thereby saving some power. Alpha IP being the heart of the chip, operates at the highest frequency, operates on an intermediate voltage, let's say 2V in our example. Remember, while this IP would dissipate too much power, the performance is also critical for our design and if we lower the operating voltage of the IP, the delays of standard cells would increase, and timing closure on such high frequencies would be difficult and in the worst case, we won't be able to meet the timing spec. Also, there may be times where I don't need such high performance from the chip, and I may choose to either lower the frequency (Dynamic Frequency Scaling (DFS)), or lower the voltage (Dynamic Voltage Scaling (DVS)), or simply turn-off the power (Power Gating) or lower both the voltage and frequency (Dynamic Voltage Frequency Scaling DVFS)).

Now that we have the design perspective in place, let's go back to power domains.  How many power domains do we have here? And how do we decide? Any logical hierarchies (or a bunch of hierarchies) which have the same power plane should comprise one power domain. Let's elaborate more on that. Any logic (let's say here 2 IPs) are said to be in the same power plane iff they operate on the same voltage and have the same switchable properties.

In our example, all three IPs operate on different voltages, and therefore naturally comprise three different power planes and hence 3 different power domains! I shall elaborate on this concept later via examples. 

Power Domain View

Having understood the concept of a power domain, let's try and understand what is a voltage area. Power domain, as the definition suggests, refers to the logical view wherein we've classified every logical hierarchy and defined the properties (operating voltage, and power state table) for all the standard cells that eventually get synthesized under that logical hierarchy. Voltage area is nothing but the physical view of a power domain where we assign a physical area on the chip for the logic under a given power domain to sit physically on the chip! Confusing, I know, but read it again and you'd be able to grasp the difference. Voltage Area would always be characterized by the fact that you'd need to specify the "rectilinear coordinates" within your chip area to define one.

Voltage Area View

Let's also talk about which I believe would be the most interesting take-away from this blog. How do we handle signals crossing from one power domain to another- which leads us to the discussion of isolation cells and the level shifters, and perhaps enable level-shifters which are the combination of isolation cells and level shifters.
Any signal crossing from one a region or a power domain which is operating on voltage of let's say V1 to a power domain which is let's say operating at voltage V2 would need to be level-shifted from V1 to V2. And the special cells which help us achieve this are called level-shifters. Level-shifters are basically buffers with two power supply nets. The input supply net is connected to the voltage supply of the driver domain and the output supply net is connected to the voltage supply of the receiver domain. Where exactly should this LS be placed (whether in the driver domain or the receiver domain is another question which would be answered in a different post).

Level-shifters

Any signal crossing from a switchable domain to an on domain need to be isolated using an isolation cell to prevent any X's being propagated. Consider a signal going from power domain A (switchable) to power domain B (on). Let's say at some time the supply to be power domain is turned-off. All the outputs of power domain A would be at an unknown state and hence referred to as "X". If these X's are not isolated, the always-on supply would be corrupt with X. Most isolation cells are usually AND/OR gates where the other input is set to a controlling value (0 for AND gate, 1 for OR gate) to prevent X-propagation. We don't see any ISOLATION from the always-on domain to the switchable domain. (Ask yourself why?! :P)

Isolation Cells

On a side note: one physical voltage area may be mapped to many logical power domains provided they all have the same primary and secondary logical power supplies.

Now I'd like you to explain what all would we need for our case with Alpha, Beta and Gamma IPs to make sure signals cross from one power domain to another seamlessly (assume all permutation and combination of crossings).

Concepts to be discussed in a future post:
  • Where exactly should this LS be placed: whether in the driver domain or the receiver domain.
  • The concept of primary v/s secondary power supply.

33 comments:

  1. 1. All the 3 IPs have different operating voltages. So we will need a total of 6 level shifters.
    2. Alpha and beta are switchable so there will be isolation cells from alpha to gamma and beta to gamma. And two more for the signals crossing between alpha and beta.
    3. If we have enable level shifters, then does it mean that two of these can replace the two LS and the two Isolation cells between alpha and beta?

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    1. 1. That's correct!
      2. "Two more for the signals crossing between alpha and beta" was the trick part, and is absolutely correct!
      3. Not just between alpha and beta, but also between alpha and gamma; and beta and gamma. The only case where we won't have "just level-shifters" in our case would be from gamma to alpha and from gamma to beta.

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    2. My bad, the isolation cells between domains with different operating voltages have to be enable level shifters. Not sure though :/

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    3. Anything from off -> on needs isolation cells. Anything from off (V1) -> on (V2) needs (isolation + level shifters = ) enable level shifters.

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  2. 1. In DVS, on reducing the voltage without reducing the frequency doesn't it affect the timing?

    2. If two IPs have same operating voltage but different switching properties, then do they fall in the same voltage area?

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    Replies
    1. 1. That's the right observation and the right concern that a physical design engineer has to deal with. If ever there's such a case one would need to close timing at the lowest voltage for setup analysis, and the highest voltage for hold analysis.
      2. That is correct. I was hoping to explain this in another blog post. But since you were able to extrapolate that idea from this post itself, I don't need to write about this anymore! :) All I'd qualify your statement to would be: all IPs with the same "primary power supply and secondary power supplies" can fall under the same VA.

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    2. No, please do write about those "primary power supply and secondary power supplies"! :O

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  3. So the number of power domains has a once to one correspondence with the number of voltage supplies used( for the lack of a better term) . So if 1V, 2V, 3V are used in the design there would be 3 power domains, while there can be multiple voltage areas.

    1. Could you please explain how do you define "switching properties"?

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    1. That is correct. The design will have at least 3 power domains. But voltage area being physical entity, there may be more than 3 voltage areas in this case too!

      By switching property, I meant what all possible combinations do we have for each power domain being off/on.
      Something like:

      Use case 1: Apha off; Beta off; Gamma off.
      Use case 2: Alpha off; Beta off; Gamma on.
      and so on and so forth.

      Now we need to see what all use-cases are applicable for us. Since we said Gamma is "always-on", it means out of the 8 possible cases, only 4 would be applicable for us. If I provide more specifications, I might be able to reduce the number of applicable use-cases further. Like I say, aplha and beta would be on/off simultaneously. It means now, I have just 2 use-cases possible.

      The more appropriate term for the "use-cases" I referred above is referred to as POWER STATE TABLE (PST) and that's exactly how it's specified! :)

      Hope I was able to address your query.

      Thanks,
      Naman

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    2. Updated the word from switching property to Power State Table to make it more clear. Thank you for asking your question. :)

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    3. Thank you. That cleared the doubt I had. Another question is: You mentioned that 2 IPs having same operating voltage CAN be in same voltage area. So can I interpret your statement that, it CANNOT be in the same voltage are too? If yes, what would be the difference between the two and the the pro's and con's of the two design?

      Thanks.

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    4. Oh yes, certainly! The decision to have two disparate VAs would be dictated by physical constraints like the placement and timing. If satisfying these constraints is easier when you have 2 distinct VAs (disjoint VAs) let's say in 2 opposite corners of the chip, you might want it that way! Disadvantage would be that the power grid would be discontinuous and this is not a very robust power grid, hence susceptible to failures in silicon. Modern EDA tools also support combining disjoint VAs into 1 VA. It's an engineering call full of interesting trade-offs.

      Good question. Thanks for asking!

      -Naman

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  4. Hi Naman,
    I have few questions here:
    1. How can we map a voltage area to multiple power domains provided that they all have the same primary and secondary logical power supplies? Shouldn't it be dependent on the switchability of the power domains?
    2. Is it possible to define a power domain without any elements specified in its definition?

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    Replies
    1. Hi Vishant,
      1. No. Let's say you just have 1 voltage supply in your design. Some logic can be switchable while other IPs are, let's say, always on. In this case, all you'd need to do is create 2 power domains, but you *may* have 1 VA. And for any crossings from the switchable to always-on PD, we can easily put isolation cells. And in my experience this would be the preferable strategy to handle such a case rather than creating two distinct VAs.
      2. No, it is not possible to define a PD without defining any elements specified. I'm wondering what could perhaps be the motivation behind such a "dummy PD"? Did you require to create one? Can you share the scenario?

      Thanks,
      Naman

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  5. HI Naman,

    Why do we need level shifters? Can we replace all LS with Isolation cells? Will they serve same purpose?

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    Replies
    1. Hi Anonymous,
      No, level shifters and isolation cells serve different purposes. You need isolation cells when power to driver domain can be switched ON, while the receiver domain can still be ON.
      You need level shifters when there's a difference in the operating voltage of two interacting domains, let's say one at 1.0V while other at 1.2V.
      You may need a level shifter + isolation cell if you have crossing between (1.0V, switchable) domain to (1.2V, always ON) domain.

      Thanks,
      Naman

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    2. Hi Naman,
      Thanks for the inputs. But here I have 2 questions/ scenarios for you!

      1. Lets say I have 2 domains, Domain A (1.0V switchable), domain B (1.2 V, always on). Signal is going from A to B when A is ON. Can I use OR type Isolation cell just to change voltage swing of signal from 1 to 1.2V (assuming, ISO supply is connected to domain B). As ISO strategy is OR type, no matter what, output will be high.
      2. Do latched type Isolation cells work same as level shifters? If yes/no, please elaborate with example.

      Thanks for your time.

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    3. Good question!!

      Let's goto more deep into LS and ISO cells.

      #1: ISO
      And example for ISO cell is an AND gate with one input from Switchable domain and another input from Always-ON domain. The output obviously fans-out to Always-ON domain. If you goto transistor level of this AND gate, all transistors in this gate are designed to operate at only one voltage (ISO Cell will not have different transistors operating at different voltages). In simple words, if we have a signal going from a voltage that can be switchable to same voltage that is always-on, we only need ISO cell.

      #2: LS cell
      In most cases, a LS cell will have a back to back buffers with first buffer operating on V1 and second buffer operating on V2. Assume if we don't have the LS, the signal on V1 (1.0V) reaching V2 domain (1.2V), may not even turn on the transistor in V2 since it's operating at higher voltage.

      Likewise a 1.2V signal, on reaching 1.0V domain, will burn out the gate terminal of the transistor.

      An ISO cell cannot be used for LS purpose since transistors in ISO are operated at one voltage, unlike transistors on LS cell which are designed at different operating voltages.

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  6. Hi Naman, i have a basic question, why do we need isolation between alpha and beta and vice-versa?

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    1. Hi Leslin,
      We need an isolation from alpha to beta only and only if there's case where alpha could be OFF and beta could be ON to prevent any X-propagation into the beta domain while it's ON.

      Similarly, we'd need an isolation from beta to alpha only and only if there's a case where beta could be OFF and alpha could be ON to prevent any X-propagation into the alpha domain while it's ON.

      -Naman

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  7. How to say that particular voltage has more on supply. If we are having 2 cases
    1. more ON's and less voltage value
    2. Less ON's and high voltage value.
    in power state stable.

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  8. Hi Naman,

    We may have to insert Iso cells from on to off(like standby mode) domain because lets say if the load is high in off domain then it ensures clk/rst won't switch/toggle in the off domain thereby reducing power consumption. Does such a scenario occur?

    Thanks,
    Vinay

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    Replies
    1. ISO cells/strategy are independent to the signal (clk/rst) and load. If you have DomainA (1.0V switchable) and DomainB (1.0 always-on).

      #1: DomainA --> DomainB
      When DomainA is turned OFF, then we will propagate an 'X' to B, which is always-ON. Irrespective of the signal type, we have to have an ISO cell in either DomainA or DomainB, before this signal goes to it's load in DomainB.

      #2: From your question (DomainB --> DomainA)
      In this situation, DomainB will never turn OFF. Since it's ON always, there is no chance we propagate an 'X' to DomainA. This stands true irrespective of signal type (Clk/Set/Reset).

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  9. Hi ls should be placed in driver domain or receiver domian and why?

    Thx
    Pankaj

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    Replies
    1. The general recommendation is to place these cells in the destination domain.

      Isolation cells are typically powered by the destination domain. If they are placed in the source domain, then the designer must connect them to the destination domain power supply. This also requires isolation cells to have secondary power pins for the connection to destination domain power supply.

      For level shifters, the location generally does not matter because they need to be connected to power supplies of both source and destination domains. However, some high-to-low level shifters only require the high supply voltage. In this case, we might want to put them in the source domain.

      When an output has a large fanout, then it might make sense to place level shifters and isolation cells in the source domain. This can significantly reduce the total number of level shifters and isolation cells in the design.

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  10. How do we know that this particular signal go from switchable PD to always on PD?So we can come to know how many isolation cells do we need ??

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    Replies
    1. In modern days, this is taken care by EDA tools when they read power intent file viz. UPF and then during synthesis, power compiler can insert ISO & LS accordingly. There are other low power verification tools on top of this (which has low power assertions) to check and report if PG netlist doesn't have correct ISO/LS inserted where it was required.

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  11. How to care of situation when signal is passing from one power domain to other via always on buffer ..this will give clp power domain crossing issue..how to take care of this issue

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  12. Can you please help me understand the difference between physcial and logical power domain?

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  13. Hi Naman. Can you give me a clear difference b/w voltage domain(area) vs power domain?
    Here...in this video link below, I see that we have 3 power domains but only 2 voltage domains. I am actually confused with your statement "one physical voltage area may be mapped to many logical power domains provided they all have the same primary & secondary power supplies". Can elucidate to clear my doubt?
    https://www.youtube.com/watch?v=4ElaNv1gdH0

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  14. Say IP1 is always-on, operates at 0.7V
    Say IP2 is always-on, operates at 0.9V
    Say IP3 is switchable, operates at 0.7V
    Say IP4 is switchable, operates at 1.1V
    Say IP5 is always-on, operates at 0.9V
    Say IP6 is always-on, operates at 1.1V

    Thus, we have 3 voltage domains.
    See that IP2, IP5 can be put under one power domain. Rest of the IPs need to be put under different power domains. Hence, there are 5 power domains.
    Is my understanding correct Naman? Pls Reply!

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  15. Hello, Can you tell about where to place level shifters at receiver side or driver side ?

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