Power Domain Crossings

With all the fuss about low power designs, the implementation of multiple power domains has gained significant traction in the past decade and they still play a critical role in designing the chips which are less power hungry. The use-cases have become more complicated and keeping up with the pace, the implementation techniques have become even more intricate! 

In this post I intend to talk about the motivation for power domains, draw a distinction between two commonly confused terms- the power domain and the voltage area, and some basics which can help the newbies lay a foundation of what to expect while implementing such designs.

As we've already discussed, the basic intention to create multiple power domains is to reduce the power consumption. But how does it help? Let's take a look. Let's say your design has three IPs- Alpha, Beta and Gamma. The Alpha IP is the heart of the design and it's basically the computation engine- think of something like the ALU or the Execution Unit. Beta IP does house-keeping jobs, mostly in the support role. While Gamma IP does all the "dirty"stuff- think of something like analog IPs like the Power Management Unit. Now, one important thing to appreciate here is that these three IPs serve different purposes, at different times with a distinct level of significance. 

Let's dig a little bit deeper into this. Aplha IP does the most important task, it is critical for performance and therefore should run at the highest possible clock frequencies and therefore burns a significant chunk of the overall power consumption. Beta IP is not needed that often, and neither does any critical work, nor does it all the time! Gamma IP does the significant task of managing the power supplies and therefore needs to be always-on!

Having delineated the expectations for each IP, now it's time to delve into some technical details that would be of particular interest to a physical design engineer and let's try and understand the rationale behind it. This time we shall start from Gamma IP. Gamma IP being the analog IP (or at best a mixed-signal IP) usually operates on high voltage because analog circuits are usually more susceptible to noise. Let's say Gamma IP operates on 3V. (Unrealistic number, when it comes to modern VLSI design, but I intend to give you a relative context! :)) Beta IP is a digital IP therefore it can operate on a lower voltage, let's say 1V in our chip and it would be a switchable IP, meaning that we can turn-off the power to this IP when it's not in use, thereby saving some power. Alpha IP being the heart of the chip, operates at the highest frequency, operates on an intermediate voltage, let's say 2V in our example. Remember, while this IP would dissipate too much power, the performance is also critical for our design and if we lower the operating voltage of the IP, the delays of standard cells would increase, and timing closure on such high frequencies would be difficult and in the worst case, we won't be able to meet the timing spec. Also, there may be times where I don't need such high performance from the chip, and I may choose to either lower the frequency (Dynamic Frequency Scaling (DFS)), or lower the voltage (Dynamic Voltage Scaling (DVS)), or simply turn-off the power (Power Gating) or lower both the voltage and frequency (Dynamic Voltage Frequency Scaling DVFS)).

Now that we have the design perspective in place, let's go back to power domains.  How many power domains do we have here? And how do we decide? Any logical hierarchies (or a bunch of hierarchies) which have the same power plane should comprise one power domain. Let's elaborate more on that. Any logic (let's say here 2 IPs) are said to be in the same power plane iff they operate on the same voltage and have the same switchable properties.

In our example, all three IPs operate on different voltages, and therefore naturally comprise three different power planes and hence 3 different power domains! I shall elaborate on this concept later via examples. 

Power Domain View

Having understood the concept of a power domain, let's try and understand what is a voltage area. Power domain, as the definition suggests, refers to the logical view wherein we've classified every logical hierarchy and defined the properties (operating voltage, and power state table) for all the standard cells that eventually get synthesized under that logical hierarchy. Voltage area is nothing but the physical view of a power domain where we assign a physical area on the chip for the logic under a given power domain to sit physically on the chip! Confusing, I know, but read it again and you'd be able to grasp the difference. Voltage Area would always be characterized by the fact that you'd need to specify the "rectilinear coordinates" within your chip area to define one.

Voltage Area View

Let's also talk about which I believe would be the most interesting take-away from this blog. How do we handle signals crossing from one power domain to another- which leads us to the discussion of isolation cells and the level shifters, and perhaps enable level-shifters which are the combination of isolation cells and level shifters.

Any signal crossing from one a region or a power domain which is operating on voltage of let's say V1 to a power domain which is let's say operating at voltage V2 would need to be level-shifted from V1 to V2. And the special cells which help us achieve this are called level-shifters. Level-shifters are basically buffers with two power supply nets. The input supply net is connected to the voltage supply of the driver domain and the output supply net is connected to the voltage supply of the receiver domain. Where exactly should this LS be placed (whether in the driver domain or the receiver domain is another question which would be answered in a different post).

Level-shifters

Any signal crossing from a switchable domain to an on domain need to be isolated using an isolation cell to prevent any X's being propagated. Consider a signal going from power domain A (switchable) to power domain B (on). Let's say at some time the supply to be power domain is turned-off. All the outputs of power domain A would be at an unknown state and hence referred to as "X". If these X's are not isolated, the always-on supply would be corrupt with X. Most isolation cells are usually AND/OR gates where the other input is set to a controlling value (0 for AND gate, 1 for OR gate) to prevent X-propagation. We don't see any ISOLATION from the always-on domain to the switchable domain. (Ask yourself why?! :P)

Isolation Cells

On a side note: one physical voltage area may be mapped to many logical power domains provided they all have the same primary and secondary logical power supplies.

Now I'd like you to explain what all would we need for our case with Alpha, Beta and Gamma IPs to make sure signals cross from one power domain to another seamlessly (assume all permutation and combination of crossings).

Concepts to be discussed in a future post:

• Where exactly should this LS be placed: whether in the driver domain or the receiver domain.
• The concept of primary v/s secondary power supply.

Integrated Clock and Power Gating

Clock Gating and Power Gating are two most commonly used design methods to save dynamic and leakage power respectively. How about integrating the two solutions such that they complement each other? In this post, I will talk about a simple way to do so.

Clock Gating is accomplished by using Clock Gating Integrated Cell (CGIC) which gates the clock to the sequential elements present in its fan-out when the enable signal is logic 0. Power Gating structures may be of two types: Simple Power Gating and State Retention Power Gating. Using the former technique, the output of the logic gates slowly leaks the charge at the output and thereby when the SLEEP signal is de-asserted, one cannot predict the logic value at the output. The latter technique is able to retain the state at the output which was last present before asserting the SLEEP signal.

Let's take up a few plausible scenarios:

• Case I - Normal Case: Which employs  only conventional clock gating. It is depicted in the figure.

 

• Case II - When one does not need to retain the states of the combinatorial cells or the sequential elements. One possible scenario could be in the case of a standalone IP, which is not comunicating with any other IP on the SoC. Here one can use thee simple power gating where the SLEEP signal is derived from the CGIC itself using a latch, as depicted in the figure below. Doing so, we would save both dynamic and leakage powers. 

• Case IIII - When one does not need to retain the states of the combinatorial cells, but the sequential outputs need to be safe-stated. Possible use-case could be where only the sequential outputs communicate with other IPs on the SoC. This can be accomplished by using State Retention Flip Flops instead of the conventional flip-flops.
• Case IV - When both the combinatorial cells and the sequential cells interact with other IPs. But the previous value need not be required. Since it is a classic case of interaction between "switchable power domain" with" always ON", it entails the use of isolation cells between such power domain crossings. It must be noted that in such a case, isolation cell would always be present in the always  ON power domain, i.e., it would receive it's VDD supply from the always ON power domain supply. This is because, when the switchable power domain in OFF, the isolation cell can function only if receives the power supply! 

Isolation Cells can be simple cells like AND or an OR gate, which receive one input in a way that, irrespective of the second input coming from the switchable power domain, the value would be controllable. For example, logic 0 for AND gate and logic 1 for an OR gate. I will try to take this up in a separate post.