Integrated Clock and Power Gating

Clock Gating and Power Gating are two most commonly used design methods to save dynamic and leakage power respectively. How about integrating the two solutions such that they complement each other? In this post, I will talk about a simple way to do so.

Clock Gating is accomplished by using Clock Gating Integrated Cell (CGIC) which gates the clock to the sequential elements present in its fan-out when the enable signal is logic 0. Power Gating structures may be of two types: Simple Power Gating and State Retention Power Gating. Using the former technique, the output of the logic gates slowly leaks the charge at the output and thereby when the SLEEP signal is de-asserted, one cannot predict the logic value at the output. The latter technique is able to retain the state at the output which was last present before asserting the SLEEP signal.

Let's take up a few plausible scenarios:

• Case I - Normal Case: Which employs  only conventional clock gating. It is depicted in the figure.

 

• Case II - When one does not need to retain the states of the combinatorial cells or the sequential elements. One possible scenario could be in the case of a standalone IP, which is not comunicating with any other IP on the SoC. Here one can use thee simple power gating where the SLEEP signal is derived from the CGIC itself using a latch, as depicted in the figure below. Doing so, we would save both dynamic and leakage powers. 

• Case IIII - When one does not need to retain the states of the combinatorial cells, but the sequential outputs need to be safe-stated. Possible use-case could be where only the sequential outputs communicate with other IPs on the SoC. This can be accomplished by using State Retention Flip Flops instead of the conventional flip-flops.
• Case IV - When both the combinatorial cells and the sequential cells interact with other IPs. But the previous value need not be required. Since it is a classic case of interaction between "switchable power domain" with" always ON", it entails the use of isolation cells between such power domain crossings. It must be noted that in such a case, isolation cell would always be present in the always  ON power domain, i.e., it would receive it's VDD supply from the always ON power domain supply. This is because, when the switchable power domain in OFF, the isolation cell can function only if receives the power supply! 

Isolation Cells can be simple cells like AND or an OR gate, which receive one input in a way that, irrespective of the second input coming from the switchable power domain, the value would be controllable. For example, logic 0 for AND gate and logic 1 for an OR gate. I will try to take this up in a separate post.

State Retention Power Gating

The post titled Power Gating demonstrated the implementation of a Power Gating Cell and how it helps in minimizing the leakage power consumption of an SoC. Make sure you go through it once more. The basic rationale is to cut the direct path from the battery (VDD) to ground (GND). Though efficient in saving the leakage power, the implementation discussed suffers from one major drawback! It does not retain the state! That means, once power of the SoC is restored, the output of the power gated cell goes to 'X'. You can't really be sure whether it is logic 1 or a logic 0. Do care? Yes! Because if this X propagates into the design, the entire device can go into a metastable state! In order to prevent such a disastrous situation: the system software can simply reset the SoC. That would boot-up from scratch and make sure that all the devices are initialized. 

This means, every time I decide to power gate a portion of my SoC, I'll have to reset that power gated portion once power is returned. This imposes a serious limitation to the application of the Power Gate discussed in the last post. How about designing one power gate which retains the state? But convince yourself that in order to do so, you'd need to spend, though small, some leakage power. Let's call this structure: State Retention Pseudo Power Gate. The term "pseudo" signifies that it would consume a little leakage power contrary to the previous structure which doesn't. But at the same time, you no longer need to reset the power gated portion of the SoC, because the standard cells retain their previous data!! Enough said! Let's discuss the implementation.

The above circuit has two parts. 

• The one inside the red oval is same as the normal power gating structure. 
• The one inside green box (on the right) is the additional circuitry required to enable this device to retain it's state.

Operation: Let's say before going into the SLEEP mode, the device had the output as logic 1. After entering the SLEEP mode (power off), the sleep transistors come into action and cut the power and ground rails of the device and hence save the leakage power. But the logic on the right (in green rectangle) is still ON! The output of the inverter would now become OUTPUT', i.e., logic 0. This would in turn enable the PMOS transistor Q1 and output would be restored back to logic 1.

Same is true when the output would be logic 0 before power gating. In that case the NMOS transistor Q0 would come into action to help the output node retain it's data.

Note that: All this while, when the device is in sleep mode, the output node would continue to leak. By adding the additional circuitry, as demonstrated, we are basically trying to create a feedback loop, which again helps in retaining the state. The hit, of course, is the leakage power of 4 transistors. However, the standard cell logic (in red oval) is usually bulky. Even a simple 2-input NAND gate has 4 transistors itself. And higher order input would have more! Same technique can be applied to any sequential device like a Flip Flop, latch or even a clock gating integrated cell.