Note from the Author

Hello folks!

In the last two days, I have come across many blogs which have used my content. 

While I feel glad that these guys have chosen my content to publish and I'm quite sure many people must have reaped benefits from it, it does hurt me to see the content- exactly same words (with even the same font!), same figures/pictures being used- without even acknowledging the source. I also understand that the end goal of all these people (including me) might be the same which is to enlighten the budding VLSI engineers, but I would urge these guys to at least acknowledge the source.

 

To name a few: 

http://vlsi-doubts.blogspot.in/2013_12_01_archive.html

http://articlesece.blogspot.in/search/label/VLSI%20SoC%20Design%20Concepts

In retrospect, in case anyone feels that any material on this blog is inappropriate, I would urge you to feel free to drop me a mail at my.personal.log@gmail.com and I assure you that I would take necessary action, even it if means completely obliterating the post or perhaps even the blog, at the earliest.

Thanks!

Regards,

Naman Gupta

Problem: Sequential Element

Another problem for you!

Consider the following circuit. Assume that each inverter takes 1 time unit for a low-to-high or high-to-low transition. Assume that it takes 1 time unit for a pull-up path or pull-down path to pull-up or pull-down respectively. Ignore any leakage effects. Assume VDD >> VT. Also assume that there is no skew between CLK and CLK_BAR and assume that rise/fall times on all signals are zero.

1. What type of sequential element is the above circuit? (Hint: Plotting the X, Y and Q with respect to the waveform of CLK and D might help you in finding the answer.)
2. What is the propagation delay of this sequential element?

Source: 

Massachusetts Institute of Technology

Dept. of Electrical Engineering and Computer Sciences

Analysis and Design of Digital Integrated Circuits- Fall 2003, Quiz #2

Prof. Anantha Chandrakasan

Problem: Energy Consumption

I came across an interesting problem and thought I would share it with you folks:

 

A battery-operated 65nm digital CMOS device is found to consume equal amounts (P) of dynamic power and leakage power while the short-circuit power is negligible. The energy consumed by a computing task, that takes T seconds, is 2PT.
 

Compare two power reduction strategies for extending the battery life:

• Clock frequency is reduced to half, keeping all other parameters constant.

• Supply voltage is reduced to half. This slows the gates down and forces the clock frequency to be lowered to half of its original (full voltage) value. Assume that leakage current is held unchanged by modifying the design of transistors.

Please post your answers as comments to this blog post.

 

Source: Dynamic and Static Power in CMOS. A Presentation by Vishwani D. Agrawal, Auburn University, USA and Srivaths Ravi,Texas Instruments India.

 

The Legend of Synchronizer

Long time ago, there were two warriors: Clock Domain 1 and Clock Domain 2. Each had their respective clocks CLK-1 and CLK-2 which they contended to be the master of their own will! The frequency and the phase relationship of the two clocks were independent of each other.

In absence of any such relationship, there is a possibility of the two clock edges being precariously close that could in turn cause a timing violation. The metastable output of the FF-2 could pass on to the entire system and disrupt the entire computation of the chip. FF-S steps in to resolve the impasse and urges the two clock domains to have a deterministic relationship between their clocks.

But the two clock domains refuse to budge! Neither of them were willing to curtail the freedom of their clocks which they deeply cherished! 

Here the FF-S sacrifices its own output and offers a solution to the clock domains.

That's how the FF-S ensured the prosperity of the entire SoC by suffering a metastability at it's own output. And since then it's been called The SYNCHRONIZER Flop! Note that it is necessary to connect the synchronizer flop's clock to the clock of the second domain.

Over the years, there's been a practice of using up to three such synchronizer flops depending upon the application.

I'll talk about the concept of Mean Time Before Failure (MTBF) which is very closely related to metastability shortly.