Another problem for you!
Consider the following circuit. Assume that each inverter takes 1 time unit for a low-to-high or high-to-low transition. Assume that it takes 1 time unit for a pull-up path or pull-down path to pull-up or pull-down respectively. Ignore any leakage effects. Assume VDD >> VT. Also assume that there is no skew between CLK and CLK_BAR and assume that rise/fall times on all signals are zero.
Consider the following circuit. Assume that each inverter takes 1 time unit for a low-to-high or high-to-low transition. Assume that it takes 1 time unit for a pull-up path or pull-down path to pull-up or pull-down respectively. Ignore any leakage effects. Assume VDD >> VT. Also assume that there is no skew between CLK and CLK_BAR and assume that rise/fall times on all signals are zero.
- What type of sequential element is the above circuit? (Hint: Plotting the X, Y and Q with respect to the waveform of CLK and D might help you in finding the answer.)
- What is the propagation delay of this sequential element?
Source:
Massachusetts Institute of Technology
Dept. of Electrical Engineering and Computer Sciences
Analysis and Design of Digital Integrated Circuits- Fall 2003, Quiz #2
Prof. Anantha Chandrakasan
