I came across an interesting problem and thought I would share it with you folks:
A battery-operated 65nm digital CMOS device is found to consume equal amounts (P) of dynamic power and leakage power while the short-circuit power is negligible. The energy consumed by a computing task, that takes T seconds, is 2PT.
Compare two power reduction strategies for extending the battery life:
- Clock frequency is reduced to half, keeping all other parameters constant.
- Supply voltage is reduced to half. This slows the gates down and forces the clock frequency to be lowered to half of its original (full voltage) value. Assume that leakage current is held unchanged by modifying the design of transistors.
Please post your answers as comments to this blog post.
Source: Dynamic and Static Power in CMOS. A Presentation by Vishwani D. Agrawal, Auburn University, USA and Srivaths Ravi,Texas Instruments India.
