Puzzle: Stuck-at Fault

Around 2.5 years back, I had posted a Puzzle: Stuck-At Fault on this blog where I had asked to find the input vector to detect a particular stuck-at fault in a given circuit. This puzzle is exactly the same problem, but with a more complex circuit.

Assuming a SINGLE STUCK-AT FAULT MODEL, could you please help me with the input vector to detect:

1. A Stuck-at-0 fault at node L.
2. A Stuck-at-1 fault at node L.

Please post your answers in the comment section below.

Channel Length vs Gate Length

Till a few months back, I assumed that channel length and gate length were same terms used interchangeably. However, one of the classes that I took at USC cleared this doubt and I'm very thankful to my professor for explaining the subtle difference between the two.

The figure above shows the cross-section of an NMOS with it's source, drain, gate. Let's talk about the difference between gate length, channel length and the diffusion length.

While fabricating a MOS device, typically the poly gate is grown first using the minimum feature size mask which is characteristic of a particular technology node. After this, the source and drain are formed by ion-implantation of Phosphorus (n+). This is referred to as self-aligned process. After ion-implantation, there is some side diffusion of the implanted ions because of which, the n+ region extends up to a small width below the gate. This is referred to as the diffusion length or the diffusion width. The effective distance between the drain and the source where the channel would eventually be formed and the actual length an electron would travel from source to drain is called the Effective Channel Length! I encourage you to read up more about the steps in CMOS Fabrication for better understanding. 

As evident from the above figure:

Channel Length = Gate Length - 2 x (Diffusion Length)

Well, that was theory! Now some practical discussion. :)

When we say that we have let's say a 28 nm technology node. Which of the above would be 28 nm? Well, it would be the GATE LENGTH! As pointed above, gate corresponds to the minimum feature size mask which is characteristic of a particular technology node!

Now, let's say, this NMOS is operating in the saturation regime, and there's no pinch off yet. If you wish to find the saturation current flowing through the device, you'll have to use the channel length in the formula for the drain current which is a quadratic function of the gate-to-source voltage. 

How do we find this channel length? For older technology nodes (like 250 nm), this diffusion used to be negligible as compared to the gate length. However, for advanced sub-micron technology nodes, the side diffusion length is typically 10% of the gate length. (Actual numbers may vary from one manufacturer to another). So, for 28 nm technology node, you might expect the actual channel length to be in the order of 20-22 nm.

Drain and the Source of MOS Transistors

How does one decide which terminal of the MOS Transistor is the Source and which terminal is the Drain?

While most of us are taught one basic rule in our introduction classes to the CMOS Transistor: The source of an NMOS is typically at the lowest potential while the source of a PMOS transistor is at the highest potential. 

While this rule is correct, there got to be a plausible technical explanation behind this nomenclature. In this post, I'll discuss that explanation.

First of all one must appreciate the fact that unlike BJT, MOSFET is a symmetric structure. By this, I mean that any terminal can act as drain or source depending upon the voltage applied on that particular terminal. In NMOS: Source is the terminal which is at the lowest potential. In PMOS, Source is the terminal with the highest potential. Now, the question arrives why did we choose to call a particular terminal as source or drain. Read on.

In NMOS, the majority charge carriers are the electrons. If you've followed the physics behind the transistor operation, you'd know that current in an NMOS flows from Drain to Source. Alternatively, electrons flow from the source to drain. Source is therefore the "reservoir" or "source" of electrons which get "drained" at the Drain! That's where the terminology comes from. Therefore, the source of electrons in an NMOS has to be connected to the lowest potential, that being the VSS. And Drain to the higher potential, which could perhaps be VDD.

In PMOS, the majority charge carriers are the holes. Holes will flow from higher potential to a lower potential. Higher potential terminal would act as the "source" of holes. That would therefore be VDD. These holes would get "drained" at a lower potential, which could perhaps be VSS. Therefore, for PMOS, higher potential terminal would be the Source, and lower potential terminal would be the drain!