Puzzle: CMOS

Let's say you have a 2-input CMOS NAND Gate. Due to some design pre-requisite, it is always ensured that the input A goes from low-to-high before the input B. 

In order to optimize the delay of the NAND Gate, which on out of the 2 configurations would you choose and why?

Puzzle: Fixing Timing Violation

Timing Violation can manifest due to a plethora of reasons. And it is important for an STA Engineer to understand the violating path and model the constraints properly before providing them to the Synthesis/PnR tools for optimization. Unnecessary optimization should be avoided because:

• To save on the die area;
• To save on the leakage power;
• To prevent unnecessary congestion.

The figure below shows a scenario. Assume the clock period to be 8ns and the setup time of the capture flop (here, FF3) be 0ns and the clock-to-Q delay of the launch flops (here, FF1 & FF2) be 0ns. The violating path is shown in the figure. The negative slack is 1ns. 

How would you fix the above violation? Please note that there are many possible solutions; but one only solution adheres to the above discussed constraints of leakage power, area and congestion.

Clock Gating Check

In the post, Clock Gating, I described the rationale behind gating the clock and the repercussions one might face if the clock is not gated properly. 

To recapitulate, for clock gating:

• Rationale: Saving the dynamic power of the Flip Flops.
• Repercussion (if not done properly): Glitch in the clock tree; and hence metastability at the flop outputs. 

Clock can be gated in many ways. Some require more precautions than others. We model those "precautions" in the form of constraints for the EDA tool to understand. And that's what are called Clock Gating Checks.

Let's consider them all one by one.

• AND Gate based Clock Gating: As we discussed in the last post, to prevent any glitch from being propagated at the output of AND Gate based clock gating, the enable signal must switch only when the clock is low. Consider the following scenario and note the setup and hold checks for it. 

 

The same scenario also appeared in the puzzle titled: Identify Issue with Circuit Topology. The solution for problem, and for the above constraint to be met would be that the launching flop should be a negative edge triggered flop. 

You might argue that a positive edge triggered flop with sufficient delay might also solve the purpose. But note that, that scenario would vary with the PVT corners. It might very well be a case that the delay is sufficient in the worst case PVT, and not in the base case PVT; which would be very difficult to achieve!

• OR Gate Based Clock Gating: To prevent any glitch being propagated to the output of an OR gate based clock gating, the enable should toggle only when the clock is high. The figure below depicts the setup and hold checks in an OR gate based clock gating.
  

We shall discuss the clock gating checks for a multiplexer in the next post. Till then, try to grasp this post!