February 09, 2013

Puzzle: CMOS

Let's say you have a 2-input CMOS NAND Gate. Due to some design pre-requisite, it is always ensured that the input A goes from low-to-high before the input B. 


In order to optimize the delay of the NAND Gate, which on out of the 2 configurations would you choose and why?




3 comments:

  1. Conf 2 , as it puts the latest incoming signal closer to the output Y, there by avoiding charging of node capacitance at the junction of the two transistors- this reduces delay.

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  2. That is absolutely correct!! Thanks for posting the answer and sharing the precise explanation!

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  3. Elmore Delay Model!

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