Let's say you have a 2-input CMOS NAND Gate. Due to some design pre-requisite, it is always ensured that the input A goes from low-to-high before the input B.
In order to optimize the delay of the NAND Gate, which on out of the 2 configurations would you choose and why?
Conf 2 , as it puts the latest incoming signal closer to the output Y, there by avoiding charging of node capacitance at the junction of the two transistors- this reduces delay.
ReplyDeleteThat is absolutely correct!! Thanks for posting the answer and sharing the precise explanation!
ReplyDeleteCan you explain in detail as to how config 2 is right ?
DeleteElmore Delay Model!
ReplyDeleteCan you please explain the reason behind this?
ReplyDeleteIn config1, A arrives first and wants to drive load cap and junction cap to zero but can't since it's not connected to GND until B goes high.
DeleteIn config2, A arrives first and drives the junction cap to zero quickly since its connected to GND and then B arrives and it only has to drive the load cap to zero, hence the lower delay in config2.
This is why it's preferable to place critical signals closer to output.