Routing: Basics

Routing process determines the precise paths for nets on the chip layout to interconnect the pins on the circuit blocks. Before discussing further, it would be prudent to discuss where does Routing actually fit in the Physical Design flow.

After Synthesis (the conversion of RTL to gate-level netlist), the blocks and the instances are Placed, which, to some extent, is governed by the Floorplan. After Placement, Clock Tree is synthesized followed by Routing of the signal nets. The following flow chart summarizes the Physical Design Flow.

Objectives of the Routing Process:

• To determine the necessary wiring, e.g., net topologies and specific routing segments, to connect these cells while respecting constraints like design rules.
• To Optimize routing objectives, e.g., minimizing total wire length and maximizing timing slack.

Routing is further divided into many subtypes:

• Global Routing: It defines the routing regions and generates a tentative route for each net. Each net is assigned to a set of routing regions. However, it does not specify the actual layout of wires and it not sensitive to DRV violations.

• Detailed Routing: For each routing region (defined during Global Routing), each net passing through that region is assigned to particular routing tracks. The actual layout of wires is specified. It also tries to fix all DRV violations in the design.

Puzzle: Divide by 3 Counter with 50% DC

It is pretty simple to make a clock divider with odd frequency division (let's say 3 or 5). But it doesn't have 50% duty cycle. Some modifications are essential to achieve that 50% duty cycle. You might argue, why so much fuss about 50%? To give you an insight into it, consider the following divided waveform with 66% DC:

As you can note from the above waveforms: 

• NEG-TO-POS arc (i.e. any path launching from a negative edge triggered flop and being captured at positive edge triggered flop) would have least time to meet the setup time requirement and hence can be critical. 
• On the other hand, POS-TO-POS and NEG-TO-NEG are so much relaxed. 

Same would be true for a divider with 33% duty cycle as well. So, it is preferable to use a divided clock with 50% duty cycle.

Can you design such a circuit which takes a clock signal of frequency f, and outputs another clock signal of frequency f/3 with 50% duty cycle?

Power Gating

Power Gating is yet another effective implementation employed in Low Power Designs. Unlike Clock Gating, which saves the dynamic power, Power Gating saves the leakage power. As we move from micron (i.e. greater than 90nm) technology nodes to sub-micron (i.e. less than 90nm) technology nodes, leakage power dissipation dominates the dynamic power dissipation. It is therefore employed very frequently in modern SoCs. We shall talk about the structure of a power gate in this post.

Consider any CMOS digital logic circuit consisting of Pull-Up Network (made from PMOS transistors) and Pull-Down Network (made from NMOS transistors), as shown in the figure. 

At any point of time, if a direct path would exist from the power supply (VDD) and the ground (GND), the circuit would continue to dissipate leakage power. What is the possible turnaround? One can gate the power and ground terminals from the circuit when it is not intended to be used. That's what is accomplished by a power gate! Let's take a look at the circuit.

• During normal operation, SLEEP = 0. Both the PMOS and NMOS Sleep Transistors (in blue and green respectively) are ON. And we have Virtual Power Rails and Virtual Ground which ensure normal circuit operation. 
• However, during periods of low activity, SLEEP = 1. Hence the Sleep Transistors turn OFF. And a direct path from power rails to ground is broken and hence no leakage power is dissipated due to the Pull-up and Pull-down networks.

Note that, during normal operation, Sleep Transistors contribute to some extra leakage power because they are still ON. Though, the leakage power due to these two transistors would be extremely small compared to that of the Pull-up and Pull-down networks, nevertheless, these transistors are custom designed in a way such that they have high Vt (the threshold voltage) to reduce any excess leakage power during normal mode of operation. 

Puzzle: Identify the Issue with Circuit Topology

With the symbols having their usual meaning, identify the issue with this circuit topology.

[Hint]: Think from the timing perspective, and not the functional perspective.

You may answer the following:

• Issue with the topology.
• And in which kind of timing violation will the issue manifest itself while timing analysis.
• Possible modification(s) to solve the issue.

Clock Gating Integrated Cell

In the post, Clock Gating, we discussed the need for Clock Gating for Low Power Design Implementation. Clock being the highest frequency toggling signal contributes maximum towards the dynamic power consumption in the SoC even when the flops that are being fed by the clock are not changing their state. So, it is practical to gate the clock from reaching the set of registers or maybe some block in a design to save on the dynamic power consumption.

 You can relate it to the Standy mode in your PCs. In standy mode, only a sub-system of your entire SoC is working. Hence to save on the power consumption, one can employ clock gating. (Or maybe some other power saving methods, that we will discuss later).

Instead of using an AND or an OR gate for clock gating which is vulnerable to glitchy output, design engineers prefer to use the Clock Gating Integrated Cell (CGIC) to completely obviate the problem. Here's the circuit of a CGIC:

As evident from the above waveforms, if enable EN of the CGIC is logic-1, CGIC passes on the clock at the output without any glitch. And if EN is at logic-0, the outpiut is gated, i.e. no clock at the output and hence saving on the dynamic power consumption in the device.

Passing Arguments to an User-Defined Proc in Tcl

Passing arguments to any procedure is a very common scripting style. In this post we will discuss two ways one can pass arguments to any procedure in Tcl.

Just like the last post, Reading from and writing to a file in Tcl, the text in black represents tcl commands. Text in red represents user-defined variables.

The conventional way to pass arguments to a user-defined procedure (palindrome, in this case) in Tcl is:

proc palindrome { arg1 arg2 } {

<body of the proc using $arg1 and $arg2>

}

The above proc is then called like: palindrome <arg1> <arg2>

The order of passing these arguments need to be maintained.

The above approach works fine. However, when the number of arguments is large, one needs to remember the relevance of each argument and their order of occurrence.

Here's a more versatile way of passing the arguments:

 proc palindrome { args } {
    variable args_list {}
    set valid_switches [list "-description_arg1" "-description_arg2"]
    parse_proc_args $args $valid_switches palindrome

    set arg1           [cdr [assoc "description_arg1"          $args_list]]
    set arg2           [cdr [assoc "description_arg2"          $args_list]]
<body of the proc using $arg1 and $arg2>
}

The above proc is called like: palindrome -description_arg1 <arg1> -description_arg2 <arg2>

Here you can always associate the "description_arg1" keyword with arg1 and so on. Moreover, it is not necessary to call arg1 before arg2.

You can also use: palindrome -description_arg2 <arg2> -description_arg1 <arg1>

  All you gotta make sure is that you associate the arguments with the corresponding description switch!