IR Drop Analysis - II

A couple of years back, I wrote about IR Drop Analysis in one of my earlier posts. Fortunately. I got to work on IR Drop Analysis more extensively over past couple of months, and I thought I'll share my perspective gained from the work in form of a new post! 

During static timing analysis, the voltage (Vdd) at all the devices is assumed to be a constant. Similarly, the ground pin (Vss) is assumed to be held at a constant 0 V. In reality, this voltage is not a constant and it varies with time. This variance in the voltage on the power and ground lines is referred to as Power noise and Ground bounce respectively. This noise is collectively referred to as Power noise. IR drop on the data path cells will impact setup-timing, while on the clock cells, it may cause both setup and hold timing problems. 

Voltage Droop and Ground Bounce

The robustness of power grid needs to be tested thoroughly under various modes of operation. These two modes are referred to as Static IR Drop and Dynamic IR Drop.

I.                    Static IR Drop

Static IR drop takes into account the average current drawn from the power grid assuming average switching conditions. This analysis is performed early in the design cycle when simulation vectors are not quite available to the design teams. Instead, static IR drop relies on average data switching to compute the average current drawn from the power grid over 1 clock cycle. 

Static IR drop can highlight power grid weakness in the design. Static IR drop violations spread all across the design point to the fact that the power grid needs to be re-designed to reduce the overall power grid resistance. There may be cases where static IR drop violations may be concentrated around the regions with inherent power grid weaknesses- like the regions with one-sided power delivery- around the floorplan boundary, around the macros, within the macro channels.

Power distribution network is usually a mesh in top most metal layers with strategic drop downs to lower metal layers which eventually feed the standard cells. Power is routed in top metal layers to keep the resistance minimum which will also ensure uniform power delivery to all parts of the chip.

If PDN is not design carefully, it will result in creation of one-sided power delivery which will create areas of high resistance.

Power grid strengthening can be achieved by:

•  Making the power grid denser by adding wider PG straps to improve the current conductivity.
• Incrementally inserting via or via ladders along the power grid to drop from a higher metal layer to lower metal layers.

Increasing the clock frequency (with or without optimizing for higher frequency target) has a direct impact on static IR drop, because it increases the average current drawn from the power grid.

Lowering the clock frequency decreases the average current, and hence also decreases static IR drop

II.                     Dynamic IR Drop

Dynamic IR drop, also known as Instantaneous Voltage Drop (IVD), is the instantaneous drop in the voltage rails because of high transient current drawn from the power grid. Dynamic IR drop takes into account the instantaneous current drawn from the power grid in a switching event. This analysis is usually performed towards the end of design cycle when design team has the simulation vectors available from their functional or test pattern simulations. This mode of analysis is most time consuming, but nevertheless critical to ensure no surprises on silicon.

Dynamic IR drop is a function of:

• Power Distribution Network (PDN): Just like the static IR drop, weak PDN affects dynamic IR as well. A weaker power grid is not equipped to meet the peak current demand by switching standard cells and it exacerbates the dynamic IR drop.
• Simultaneous Switching: Higher simultaneous switching of standard cells tends to create local hotspots where peak current demand is higher, which causes voltage to drop in these hotspots.

Potential ways to mitigate dynamic voltage drop are as follows:

• Augmenting the power grid to minimize PG resistance- Adding more power/ground straps facilitate better distribution of current to the standard cells, thereby reducing the susceptibility to dynamic IR drop. 
• Cell Padding- Another effective way to reduce dynamic IR drop is to space apart cells which switch simultaneously to reduce the peak current demand from the power grid. This works especially well for clock cells which tend to display temporal switching and spatial locality.

Cell Spacing to solve instantaneous voltage drop

• Downsizing- Downsizing cells reduces the instantaneous current demand, with a possible downside on setup timing.

Downsizing cells to solve instantaneous voltage drop

• Splitting the output capacitance- The amount of current drawn from the power grid is directly proportional to output capacitance that’s being driven. Splitting the output capacitance can reduce the peak current demand, and also improve timing in most cases.

Split output capacitance to reduce peak current drawn from the power grid

• Inserting decap cells- Decap cells are decoupling capacitors that tend to act as charge reservoirs that can supply current to the standard cells in event of high requirement, especially when there’s simultaneous switching of cells in a local region. However, just like any capacitor, decaps tend to be leaky and add to the leakage power dissipated in the design. 

Inserting decaps to minimize dynamic voltage drop

With shrinking geometries, designs are moving from gate-dominated designs to wire-dominated designs. Also, the operating frequencies have been increasing. More signal wires mean lesser routing resources for the power distribution network. Moreover, lower technology nodes allow higher packing density of standard cells. Higher frequencies cause higher switching resulting in higher voltage droop and higher ground bounce.

Due diligence is necessary not just to design the power grid but also to analyze and fix the dynamic IR drop violations to avoid seeing any timing surprises on silicon.

IR Drop Analysis

Just yesterday, I got a question from one of our readers Lakshman Yandapalli. I thought it would be nice to write a blog post for you all!

Let's start with some background as to what indeed is the IR drop analysis.

When we talk about standard cells, we usually talk about the logical pins, let's say, A and B for the inputs and Z for outputs. What we do miss stating explicitly are the power/ground pins: the VDD and the VSS. These connections are usually implicit from the context (unless of course if you have a Muti-voltage design! Let's save this story for some other post).

IR drop is the voltage drop in the metal wires consituting the power grid before it reaches the VDD pins of the standard cells. Why do we bother about the voltage? Because the speed of the standard cell (the propagation delay) would be directly proportional to the VDD value. Higher VDD would mean faster cell, or lower propagation delay.

Now imagine that your SoC has a nominal voltage of 1V, and you closed your setup timing assuming the ideal 1V libraries. However, the IR drop of 40mV came into picture after you built the power grid, and the voltage is no longer 1V, let's say it is 0.96V. Now, with V = 0.96V, the delays of standard cells would be higher and you might see an increase in your setup-time violations!

Let's look into the factors that could cause this IR drop and how can we mitigate those factors, and what should our sign-off corners be to make sure no failures post-silicon!

While considering IR drop, you'd be concerned with two factors:

1. Static IR Drop: Dependent on the RC of the power grid connecting the power supply to the respective standard cells.

It is ALWAYS desirable to create the POWER GRID in higher metal layers. Higher metal layers would mean more wide wires, and hence would mean lower resistance. Lower resistance would mean that the IR drop would be lower, and hence lesser impact on setup-timing. 

Capacitance of metal wires would be the combination of ground and the coupling capacitance. If for some reason, you feel that the capacitance is too large, and it is indeed the reason for IR drop, it could either be because 

• Long wire length: Resulting in higher wire cap. 
• High fan-out of the net: Resulting in higher load-cap, or perhaps 
• High routing congestion in a particular area resulting in high coupling capacitance with the neighboring nets.

Now, how to mitigate the problem? You can try splitting the net so that the fan-out gets distributed (pretty much similar to building a clock tree), you can split the long wire by placing appropriate power bumps. Or you can also analyze the congestion and space the wires apart to reduce coupling capacitance!

Update: 

Simple equation representing the static IR drop would be the following:

Vstatic_drop = Iavg x Rwire

2. Dynamic IR Drop: Dependent on the switching activity of the standard cells themselves.
Switching activity of standard cells also contributes significantly to the IR drop, also known as the Dynamic IR drop. Higher would be the switching activity, in a given region, there'll be an increased demand for current from the power supply. More is the current, more would be the IR drop (which is essentially Current times the wore resistance!).
If you ever come across such a use case, you might want to space the standard cells apart so that the burden on a given bump to feed many standard cells which have high switching activity would be mitigated. 
Dynamic IR Drop is also sometimes referred to by the term of Voltage "Droop".
Update: Dynamic IR drop is contingent upon the current drawn by the standard cells, and that brings in a time-dependent variation of current into picture. Dynamic IR drop is represented by the equation:

Vdynamic_drop = L (di/dt)

Now that we have a fair understanding of IR Drop analysis, let's talk about the PVT/RC corners where one should analysis IR drop in their design.

Let's start with the RC corner.

1. RC Corner: The RC corner where the physical design engineers should analyze for IR drop would be the case when the RC product is worst. And that would indeed be the (RC)max corner, also referred to as the RCWorst corner.

2. PVT Conditions: PVT conditions would typically impact the standard cells. For IR drop analysis we would be concerned about the case where we expect the highest switching activity for standard cells. That would be the FF corner, High voltage, and high temperature.

High temperature might seem an anomaly, but higher temperature would mean higher wire resistance as well, and hence higher RC!

Last comment about IR drop analysis. It also makes sense to run IR drop analysis for the worst case setup timing check because IR drop would most probably impact only setup timing. So, designers may want to run the IR drop analysis for the RCWorst, High Temperature, SS slow and low voltage. But typically it is not done because the low voltage corner is usually already guard-banded to account for the IR drop. So, running IR drop analysis on the low voltage corner would be overly pessimistic!