IR Drop Analysis

Just yesterday, I got a question from one of our readers Lakshman Yandapalli. I thought it would be nice to write a blog post for you all!

Let's start with some background as to what indeed is the IR drop analysis.

When we talk about standard cells, we usually talk about the logical pins, let's say, A and B for the inputs and Z for outputs. What we do miss stating explicitly are the power/ground pins: the VDD and the VSS. These connections are usually implicit from the context (unless of course if you have a Muti-voltage design! Let's save this story for some other post).

IR drop is the voltage drop in the metal wires consituting the power grid before it reaches the VDD pins of the standard cells. Why do we bother about the voltage? Because the speed of the standard cell (the propagation delay) would be directly proportional to the VDD value. Higher VDD would mean faster cell, or lower propagation delay.

Now imagine that your SoC has a nominal voltage of 1V, and you closed your setup timing assuming the ideal 1V libraries. However, the IR drop of 40mV came into picture after you built the power grid, and the voltage is no longer 1V, let's say it is 0.96V. Now, with V = 0.96V, the delays of standard cells would be higher and you might see an increase in your setup-time violations!

Let's look into the factors that could cause this IR drop and how can we mitigate those factors, and what should our sign-off corners be to make sure no failures post-silicon!

While considering IR drop, you'd be concerned with two factors:

1. Static IR Drop: Dependent on the RC of the power grid connecting the power supply to the respective standard cells.

It is ALWAYS desirable to create the POWER GRID in higher metal layers. Higher metal layers would mean more wide wires, and hence would mean lower resistance. Lower resistance would mean that the IR drop would be lower, and hence lesser impact on setup-timing. 

Capacitance of metal wires would be the combination of ground and the coupling capacitance. If for some reason, you feel that the capacitance is too large, and it is indeed the reason for IR drop, it could either be because 

• Long wire length: Resulting in higher wire cap. 
• High fan-out of the net: Resulting in higher load-cap, or perhaps 
• High routing congestion in a particular area resulting in high coupling capacitance with the neighboring nets.

Now, how to mitigate the problem? You can try splitting the net so that the fan-out gets distributed (pretty much similar to building a clock tree), you can split the long wire by placing appropriate power bumps. Or you can also analyze the congestion and space the wires apart to reduce coupling capacitance!

Update: 

Simple equation representing the static IR drop would be the following:

Vstatic_drop = Iavg x Rwire

2. Dynamic IR Drop: Dependent on the switching activity of the standard cells themselves.
Switching activity of standard cells also contributes significantly to the IR drop, also known as the Dynamic IR drop. Higher would be the switching activity, in a given region, there'll be an increased demand for current from the power supply. More is the current, more would be the IR drop (which is essentially Current times the wore resistance!).
If you ever come across such a use case, you might want to space the standard cells apart so that the burden on a given bump to feed many standard cells which have high switching activity would be mitigated. 
Dynamic IR Drop is also sometimes referred to by the term of Voltage "Droop".
Update: Dynamic IR drop is contingent upon the current drawn by the standard cells, and that brings in a time-dependent variation of current into picture. Dynamic IR drop is represented by the equation:

Vdynamic_drop = L (di/dt)

Now that we have a fair understanding of IR Drop analysis, let's talk about the PVT/RC corners where one should analysis IR drop in their design.

Let's start with the RC corner.

1. RC Corner: The RC corner where the physical design engineers should analyze for IR drop would be the case when the RC product is worst. And that would indeed be the (RC)max corner, also referred to as the RCWorst corner.

2. PVT Conditions: PVT conditions would typically impact the standard cells. For IR drop analysis we would be concerned about the case where we expect the highest switching activity for standard cells. That would be the FF corner, High voltage, and high temperature.

High temperature might seem an anomaly, but higher temperature would mean higher wire resistance as well, and hence higher RC!

Last comment about IR drop analysis. It also makes sense to run IR drop analysis for the worst case setup timing check because IR drop would most probably impact only setup timing. So, designers may want to run the IR drop analysis for the RCWorst, High Temperature, SS slow and low voltage. But typically it is not done because the low voltage corner is usually already guard-banded to account for the IR drop. So, running IR drop analysis on the low voltage corner would be overly pessimistic! 

Dynamics of Scan Testing

In accordance with the Moore’s Law, the number of transistors on integrated circuits doubles after every two years. While such high packing densities allow more functionality to be incorporated on the same chip, it is, however, becoming an increasingly ponderous task for the foundries across the globe to manufacture defect free silicon. This predicament has exalted the significance of Design for testability (DFT) in the design cycle over the last two decades. Shipping a defective part to a customer could not only result in loss of goodwill for the design companies, but even worse, might prove out to be catastrophic for the end users, especially if the chip is meant for automotive or medical applications.

Scan testing is a method to detect various manufacturing faults in the silicon. Although many types of manufacturing faults may exist in the silicon, in this post, we would discuss the method to detect faults like- shorts and opens.

Figure 1 shows the structure of a Scan Flip-Flop. A multiplexer is added at the input of the flip-flop with one input of the multiplexer acting as the functional input D, while other being Scan-In (SI). The selection between D and SI is governed by the Scan Enable (SE) signal.

        Figure 1: Scan Flip-Flop

Using this basic Scan Flip-Flop as the building block, all the flops are connected in form of a chain, which effectively acts as a shift register. The first flop of the scan chain is connected to the scan-in port and the last flop is connected to the scan-out port. The Figure 2 depicts one such scan chain where clock signal is depicted in red, scan chain in blue and the functional path in black. Scan testing is done in order to detect any manufacturing fault in the combinatorial logic block. In order to do so, the ATPG tool try to excite each and every node within the combinatorial logic block by applying input vectors at the flops of the scan chain. 

Figure 2: A Typical Scan Chain

Scan operation involves three stages: Scan-in, Scan-capture and Scan-out. Scan-in involves shifting in and loading all the flip-flops with an input vector. During scan-in, the data flows from the output of one flop to the scan-input of the next flop not unlike a shift register. Once the sequence is loaded, one clock pulse (also called the capture pulse) is allowed to excite the combinatorial logic block and the output is captured at the second flop. The data is then shifted out and the signature is compared with the expected signature. Modern ATPG tools can use the captured sequence as the next input vector for the next shift-in cycle. Moreover, in case of any mismatch, they can point the nodes where one can possibly find any manufacturing fault. Figure 3 shows the sequence of events that take place during scan-shifting and scan-capture.

Figure 3: Waveforms for Scan-Shift and Capture

Shift Frequency: A trade-off between Test Cost and Power Dissipation

It must be noted that the number of shift-in and shift-out cycles is equal to the number of flip-flops that are part of the scan chain. For a scan chain with, let’s say, 100 flops, one would require 100 shift-in cycles, 1 capture cycle and 100 shift-out cycles. The total testing time is therefore mainly dependent on the shift frequency because there is only capture cycle. Tester time is a significant parameter in determining the cost of a semiconductor chip and cost of testing a chip may be as high as 50% of the total cost of the chip. From timing point of view, higher shift frequency should not be an issue because the shift path essentially comprises of direct connection from the output of the preceding flop to the scan-input of the succeeding flop and therefore setup timing check would always be relaxed. Despite the fact that higher shift frequency would mean lower tester time and hence lower cost, the shift frequency is typically low (of the order of 10s of MHz). The reason for shifting at slow frequency lies in dynamic power dissipation. 

It must be noted that during shift mode, there is toggling at the output of all flops which are part of the scan chain, and also within the combinatorial logic block, although it is not being captured. This results in toggling which could perhaps be more than that of the functional mode. Higher shift frequency could lead to two scenarios:

• Voltage Droop: Higher rate of toggling within the chip would result in drawing more current from the voltage supply. And hence there would be a voltage droop because of the IR drop. This IR drop could well drop the voltage below the safe margin and the devices might fail to operate properly. 
• Increased Die Temperature: High switching activity might create local hot-spots within the die and thereby increase the temperature above the worst-case temperature for which timing was closed. This could again result in failure of operation, or in the worst case, it might cause thermal damage to the chip.

Therefore, there exists a trade-off. It is desired to run the scan shift at a lower frequency which must be dictated by the maximum permissible power dissipation within the chip. At the same time, the shift-frequency should not be too low, otherwise, it would risk increasing the tester time and hence the cost of the chip!