June 08, 2013

Dual-Edge Triggered Flip Flop

Dual-edge triggered flip-flop is a sequential element which samples data at both positive as well as negative edges of the clock. This might come in handy in applications where the throughput is very high. It might come as a surprise that modern standard cell libraries do not have a dual edge triggered flop! Therefore, that leaves the designer to make a dual-edge triggered flop using the available standard cells. Over the years, many such designs have been proposed. While, they all work, in this post, we would discuss their pros and cons from the perspective of design, timing and power dissipation.

Implementation #1

The only possible cons with this circuit are:
  • STA would need to meet the clock gating checks at the both inputs of the multiplexer.
  • And here, the clock is used as a data which is a scenario that one would ideally like to prevent in their designs. 
  • The multiplexer would dissipate a considerable dynamic power because it's one input would be toggling at quite a high frequency.

Implementation #2
Psuedo-Dual Edge Triggered Flip Flop by Ralf Hilderbrandt 
 The possible concerns with this circuit could be:
  • The setup time and clk-to-q delay of the "dual" edge triggered flip flop would be:

    Total Setup Time = Setup time of single Flop + delay of a XOR Gate
    Clk-to-q delay      = Clk-to-q delay of a single flop + delay of a XOR Gate

    This can be quite a large value and therefore will reduce the time available for the data combinatorial logic between any two flip-flops.
  • Secondly, as the input at D would toggle (before eventually getting stable setup-time before the clock edge), and hence the XOR gates would toggle. XOR gates being the most bulky of all the primitive logic gates, the dynamic power dissipation of this flop would be quite high!

It is therefore important to discern which flop might be suitable for you. One might also look to make changes as the transistor level to achieve a better performance dual edge-triggered flip-flop. Please drop me a mail along with the weblink for such a paper in case you come across one.

1 comment:

  1. In dual edge triggered flip flop, how to avoid the problem when d flip flop set up and hold time is greater than the data switching time.