Reversible Logic Gates

Who would have thought that even digital logic gates could be reversible in nature? Well, as it turns out, there's been a lot of research already done on the subject. In this post, I would only discuss the motivation behind building reversible logic gates.

Every node can be generalized as a capacitance that would undergo charging/discharging depending upon the inputs and the logic that that particular gate has been designed to realize. And every node would dissipate charge in form of leakage power. What if someone takes the output and feeds it back to the inputs forming a "Positive Feedback" structure! In order words, one can sustain the inputs from outputs and outputs would anyway be dependent on inputs. Doing so can save a lot of leakage power and this exactly is the motivation behind building reversible logic gates. Cool, isn't it? Have a look below where C is any combinatorial logic gate.

It might be easier to appreciate the advantage of such a logic gate when many of them are attached in cascade as shown below. Here the output of one gate would sustain it's input which, in turn, would be the output of some other logic gate and it would continue on forever!! 

Enough said. Here's the paper: Efficient Building Blocks for Reversible Sequential Circuit Design by Hari, Shroff, Mahammad & Kamakoti which you can read to understand the implementation better. Please let me know in case you come across any work related to "Reversible Logic Gates".

Dual-Edge Triggered Flip Flop

Dual-edge triggered flip-flop is a sequential element which samples data at both positive as well as negative edges of the clock. This might come in handy in applications where the throughput is very high. It might come as a surprise that modern standard cell libraries do not have a dual edge triggered flop! Therefore, that leaves the designer to make a dual-edge triggered flop using the available standard cells. Over the years, many such designs have been proposed. While, they all work, in this post, we would discuss their pros and cons from the perspective of design, timing and power dissipation.

Implementation #1

The only possible cons with this circuit are:

• STA would need to meet the clock gating checks at the both inputs of the multiplexer.
• And here, the clock is used as a data which is a scenario that one would ideally like to prevent in their designs. 
• The multiplexer would dissipate a considerable dynamic power because it's one input would be toggling at quite a high frequency.

Implementation #2
Psuedo-Dual Edge Triggered Flip Flop by Ralf Hilderbrandt 

 The possible concerns with this circuit could be:

• The setup time and clk-to-q delay of the "dual" edge triggered flip flop would be:
  
  Total Setup Time = Setup time of single Flop + delay of a XOR Gate
  Clk-to-q delay      = Clk-to-q delay of a single flop + delay of a XOR Gate
  
  This can be quite a large value and therefore will reduce the time available for the data combinatorial logic between any two flip-flops.
• Secondly, as the input at D would toggle (before eventually getting stable setup-time before the clock edge), and hence the XOR gates would toggle. XOR gates being the most bulky of all the primitive logic gates, the dynamic power dissipation of this flop would be quite high!

It is therefore important to discern which flop might be suitable for you. One might also look to make changes as the transistor level to achieve a better performance dual edge-triggered flip-flop. Please drop me a mail along with the weblink for such a paper in case you come across one.

Faulty Clock Gating: How "Not" to Gate the Clock

You would come across a plethora of technical literature on clock gating and it's associated techniques. It does not come as a surprise because clock gating is the most commonly employed design technique to save dynamic power. However, many implementations are faulty, in the sense that while they indeed gate the clock, but the result in an overall increased dynamic power consumption. We would discuss one such common technique, which obviates all the power saving benefits of clock gating. You are advised to use your discretion before using it.

The basic rationale behind clock gating:

• Even when the output of a flip-flop is not toggling, owing to the transitions (and hence charging/discharging of nodes) in the internal circuitry of the flop-flop, it still continues to dissipate dynamic power when it is being fed by a clock signal.
• When the input of the flip-flop is not toggling or would not toggle, one can effectively gate the clock to that flip-flop for that particular time and save dynamic power. 

One logical implementation for the above problem statement (and this is indeed the implementation employed in many technical papers and patents) is depicted below:

Let's take a look at the above implementation. The XOR gate between the D input and the Q output of the flip-flop has been used as the enable signal for the clock gate CGIC. The logical explanation behind this is: when the output of the flop is same as input, which would be detected by XOR'ing the two, one can gate the clock to the clock gate.

Example: Let's say initially Q =1. Now D = 1, which means that t he output of the flop is destined to stay at "1" for the next cycle as well. XOR'ing these two signals: Q XOR D = 0, EN = 0 would gate the clock to the flip-flop. So, would that save power? Well, one would expect it that way. Let's take a look at why it would result in an increased power dissipation.

The circuit shown above is a trap! The actual circuit would be something like the one shown below:

• As evident from the above figure, the  XOR gate would continue to toggle for the entire time period of the clock and would become stable only "setup time" before the next clock edge. And during this entire duration, it would continue dissipating dynamic power. You might argue here that the power dissipated must be less than the power dissipated by an idle flop receiving clock. Well, that might be true for some technology, but XOR gate is the most bulky gate (among all primitive gates) and I would say that this power, if not less, would at least be comparable to that of an idle flop receiving a clock signal.
• Secondly, the circuit above uses a CGIC. Note that CGIC comprises off one latch and an AND gate, while a flop comprises  of two latches. The internal circuitry of the CGIC would continue to charge/discharge and hence dissipate power.

The sum of the above two power dissipation would over-shadow the benefits one was expecting in the first place, and hence it  is a common design trap. Beware of it.