Lock-Up Latches are important elements for any STA engineer while closing timing on their DFT Modes: specially the Hold Timing Closure of the Shift Mode. While shifting, the scan chains come into picture, which are nothing but the chains of Flops involving the output pin of one flop, connected to the Scan-Input or Test-Input pin of the other flop, and so on, forming a chain.
Now, imagine that we have two functionally asynchronous domains 1 and 2. Functionally asynchronous means that during the normal mode of operation (Functional Mode), the two domains do not interact with each other. However, very rarely do the designers have the liberty to make a separate scan chain for functionally asynchronous domains. Let's consider the following scenario: where domain 1 has the average clock latency of 3ns, and domain 2 has the average latency of 6ns. And the time period of the test clock is, let's say, 10ns.
Now, let's see the timing checks for this scenario. The output of the last flop of the domain 1 is in scan-chain and connected to the Test-Enable input of the first flop of domain 2. The check would be like:
Owing to the positive clock skew, the setup check would be relaxed, but hold would be critical. Two possible options to fix the hold timing:
- Insert the buffers, to add sufficient delay, so that hold is finally met.
- To add the Lock-Up Latch between the two flops where scan chain crosses the functional domains.
The first might not be a robust solution because the delay of the buffers would vary across the PVT Corners and RC Corners. In the worse case, there might be a significant variation in the delays across corners and you might witness closure of timing in one corner, but violation in other corner!
Second solution is a more robust solution because it obviates the above scenario. Hence see how it does it.
Timing Check would be like:
Hence, both setup and hold checks are relaxed!!
[Please note that in the above circuit, the latch is a negative level triggered latch.]
Suppose, clk1 is of very high freq . then , How would you ensure Setup time is met for lock-up latch?
ReplyDeleteHi Shubham. That is a very good question. Yes, I concede that having a lock-up latch would make your setup a half cycle check and it would become critical. But note that we placed a lock-up latch to fix the hold violation!! And if the path had been setup critical to begin with, it wouldn't have been hold critical! Because it is very unlikely that the same path would be setup as well as hold critical.
ReplyDeleteThanks for the question!
Hi, can't time borrowing for this negative level-sensitive latch relaxed our setup constraint in the case of a high freq. clock. Or time borrowing is not to be considered in this design? Correct me if I'm wrong. Thanks.
Deletetime borrowing helps when latch is capturing.
Deletetime borrowing worsens when latch is launching.
the author is right that time borrowing is a good to know in this situation as scan paths are never setup critical. You run with a 50MHz clk and so setup won't be an issue
How about inverting the clock going to FF2? it should also work the same way right?
ReplyDelete=R
From timing perspective, yes. But that would alter the functionality of the circuit. Timing often follows the design, by inverting the clock going to FF2 we would be flirting with that established norm. It might or might not be fine depending on the architectural liberty.
DeleteI think here latch is transparent when clk=0 and holds the value when clk=1 Am I correct?
ReplyDeleteOh yes. I think I missed the bubble at the clock pin of the latch. Yes, it is a negative level triggered latch, so you re right.
DeleteThanks for pointing it! :)
Hi Naman,
DeleteCould you please let me know, why are we using a latch to fix this problem ? Why not a negedge flop instead of negative level latch(lock up latch).
Set up issues may occur for the negedge Flop
DeleteIf you use a neg-level latch (lock-up latch), won't we have setup issues between the latch and FF2? The setup check will be between 2nd rising edge of CLK1 (closing edge of latch - due to time borrowing) and 2nd rising edge of CLK2. This difference is only 3ns. Isn't this too little to meet setup?
Deleteclk1-latch hold check is wrong.
ReplyDeleteIt should be from clk1 posedge to the previous negative level of latch
No.. your understanding is wrong,
Deletethe hold check of clk1-latch is between the second rise-edge of DFF1 clock and the second rise-edge of latch clock,
which equals the first edge of DFF1 clock and the first rise-edge of latch clock,
just as show in Fig 1 (red line).
you could refer to :http://tech.tdzire.com/latch-setup-and-hold-timing-checks-basics/
In my own words,
the latch is used to capture DFF1/Q output when the clock is low level.
in order to not capture the unexpected data, the DFF1/Q output should be stable till the end of latch1 clock low pulse (means till its rise edge).
which clock edge will cause DFF1/Q change?
the answer is the second rise-edge of DFF1 clock.
(westeast1984#163.com)
so the hold check should be done between the second rise-edge of DFF1 clock and the second rise-edge of latch clock
which clock edge will cause DFF1/Q unexpected change when latch want to capture the previous cycle data of DFF1 output?
Deletethe answer is the second rise-edge of DFF1 clock.
Or in the words of a solvnet article (18067):
Delete"For every setup check there are potentially two hold checks, one making sure that the data we launch now does not interfere with the previous capture and another hold check making sure that the data we launch next does not interfere with the data that we intend to capture"
golden words.
Naman , Vijay
DeleteWhat vijay says about two hold checks for every setup check , doesn't boil down to same thing when we close hold from timing closure point of view ?
Can someone explain me why are clk1-latch setup check done at the latch's falling (opening) edge? Aren't a latch's setup/hold time checks relevant only at the inactive (closing) edge (rising, in this case)? I have done paper/pencil latch internals' data flow timing diagrams to confirm this.
ReplyDeleteBecause like said in earlier comments, mentioned latch is negative edge triggered.
DeleteSo truly speaking asynchronicity of the two domains is the not main idea here. Any two heavily skewed clk domains would end up having a potential hold violation in the scan chain, requiring a lock up latch. right ?
ReplyDeleteThat's absolutely right, Niketh!
DeleteWhat about scenario where the clock skew is greater than half the clock period(+3ns in this case)? There will be hold violation again.
ReplyDeleteHi Kalpana. Your assertion is absolutely correct! But let's consider some practical numbers here. This path would be applicable for shift mode, where the clock frequencies are in the range of 20-40 MHz (Why? You might want to read this post: http://vlsi-soc.blogspot.in/2013/04/puzzle-dft-shift-frequency.html). This clock frequency translates into a clock period of 25 ns to 50 ns, which further translates into a half clock period of 12.5 ns to 25 ns.
DeleteNow, if the skew between any two domain is this much, it can only point to one thing: That the CTS engineer has done a poor job while designing the clock tree! The maximum clock latency that you may observe in a typical SoC could be upto 7-8 ns. So, the maximum global skew would never really exceed the maximum clock latency. Therefore, it is safe to say that the scenario you mentioned won't happen in a practical scenario with a good CTS!
Also, please note that 3ns in this case is not the half clock period, but the skew.
Hi Naman,
DeleteLet us consider two asynchronous scan clocks instead of two scan clocks from the same source with known skew. In this case there is a possibility of their skew being greater than half the clock period. Will this not result in hold violation ? Or even set up violation?
Hi NMN
ReplyDeleteCan you tell why have you shown a transition from START of Latch instead of END of latch transparent time, as that would be worst case setup time - I am talking in case of Latch-to-Reg path.
Thanks
Hi EE,
DeleteWhile your assertion that the worst case setup check would be from the end of latch transparent time is correct, in this post, I meant to illustrate the problem that this lock-up latch solves. The setup check from latch to register is not important here given the fact that we won't have any logic in the scan chain and shifting would be done at a slower frequency anyway.
Regards,
Nmn.
Enjoyed reading all those good set of comments. Well captured.
ReplyDeletewhat is latch transparency with in a scan chain, in what scenarios latch is transparent ?
ReplyDeleteThanks a million Naman. Excellent blog. Keep them coming.
ReplyDeletewhat if this lockup latch is reported in func mode timing result (endpoint)? is this still valid path? or something is wrong?
ReplyDeleteFor suppose if i assume clock1 latency=1.8ns and clock2 latency=2.5ns then is it
ReplyDeletepossible to hold and setup time violations? if iam wrong plz tell me.
There can never be set up and hold time violations on one single timing path if timing path is between output of one flop to input of another flop. But with launching flop and one capture flow you have 4 timing paths which might have mix of set up and hold violations.
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